Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-02-28
2003-03-04
Chung, Phung M. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S719000
Reexamination Certificate
active
06530052
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of network communications, and more particularly, to the testing of a memory of a network interface controller with a memory built-in self test (MBIST).
BACKGROUND OF THE INVENTION
Local area networks use a network cable or other media to link stations on the network. Each local area network architecture uses a media access controller (MAC) enabling network interface cards at each station to share access to the media.
Conventional local area network architectures use media access controllers operating according to half-duplex or full-duplex Ethernet (ANSI/IEEE standard 802.3) protocol using a described network medium, such as 10 BASE-T. Newer operating systems require that a network station be able to detect the presence of the network. In an Ethernet 10 BASE-T environment, the network is detected by the transmission of a line pulse by the physical layer (PHY) transceiver. The periodic link pulse on the 10 BASE-T media is detected by a PHY receiver, which determines the presence of another network station transmitting on the network medium based on the detection of the periodic link pulses. Hence, a PHY transceiver at station A is able to detect the presence of station B, without the transmission or reception of data packets, by the reception of link pulses on the 10 BASE-T medium from the PHY transmitter at station B.
Architectures have been developed enabling computers to be linked together using conventional twisted pair telephone lines instead of established local area network media such as 10 BASE-T. Such an arrangement, referred herein as a home network environment, provides the advantage that existing telephone wiring in a home may be used to implement a home network environment. However, telephone lines are inherently noisy due to spurious noise caused by electrical devices in the home, for example dimmer switches, transformers of home appliances, etc. In addition, the twisted pair telephone lines suffer turn-on transients due to on-hook and off-hook and noise pulses from the standard POTS telephones, and electrical systems such as heating and air conditioning systems, etc.
It is therefore important for a MAC to be informed of the conditions existing on a network at any time, and this is especially true in home network architectures. The status information is normally stored by the network controller in an external memory. In addition to the status information, the external memory also stores frame data and control information. The external memory, along with the PC board traces and connections, as well as parts of the logic within the network controller, comprise a memory subsystem. Failures in the memory subsystem may result from electrical or mechanical failure of any of the elements of the system and/or errors in the design of the PC board such as excessive loading or trace length.
In many networking and other products, embedded memory built-in self test (MBIST) circuits are used to test internal static random access memories (SRAMs) at speed. The MBIST is normally a simple circuit that reads or writes one memory location during each access. Recently, external RAM is being used to store the large amount of data required in modem networking applications. A number of different types of external memories, which allow burst mode capability, are being employed. These include pipeline burst SRAM, No Bus Latency (NoBL) SRAM and Zero Byte Turnaround (ZBT) SRAM.
In MBIST design, the user needs to learn any failing states in the MBIST. The information typically provided to users are the failing address and the failing locations in the memory. The user is notified of this information by shifting of the failing address and the failing locations out of a chip serially by using a single output pin. A single pin is used to minimize the pin count devoted to the MBIST and reduce costs. However, it is desirable to resume the test sequence from where it left off once an error is detected, in order to find other failing locations.
In conventional arrangements the failing address and the failing locations are stored, in addition to the operating registers, in an additional, parallel set of registers prior to the serial shifting of the MBIST results out of the chip. When the MBIST results are shifted out of the parallel set of registers and out of the chip, the primary registers will contain the information needed to resume the test sequence from the point at which the MBIST failed. Hence, the current state has been preserved.
The use of a parallel set of registers to preserve the current state at an MBIST failure to allow resumption of an MBIST following the shifting out of the failing information, is an inefficient use of chip real estate. This inefficiency is more acutely felt when the relative infrequency of the performance of an MBIST is considered.
SUMMARY OF THE INVENTION
There is a need for an arrangement and method that provides MBIST results from a chip, utilizing a minimal pin count, while also preserving the current state of the MBIST results to allow the original state to be restored, with minimal adverse impact on the chip real estate.
This and other needs are met by the present invention which provides an arrangement for performing a memory built-in self test (MBIST) on a memory and shifting the MBIST results out of a circuit, comprising an MBIST controller configured to perform a MBIST on a memory and generate MBIST results and a plurality of registers storing the MBIST results. The registers are connected together in a loop, with each register storing a different portion of the MBIST results. The arrangement includes an MBIST controller output coupled to an output of one of the registers in the register loop and at which the MBIST results are serially shifted out of the MBIST controller. Output control logic is provided that is configured to serially shift the different portions of the MBIST results through the loop of registers and to the MBIST controller output. This serial shifting is performed such that when the MBIST results are completely serially shifted out of the MBIST controller output, the different portions are returned to the same respective registers in which the different portions were stored prior to being serially shifted through the loop of registers.
The configuration of the plurality of register as a loop allows the MBIST results to be shifted out in a serial manner, but does not require the use of an additional set of parallel registers to restore the original state, thereby saving chip real estate. Instead, the looping back of the MBIST results through the registers restores each of the registers to its original state when the MBIST was stopped due to a test failure.
The earlier stated needs are also met by another embodiment of the present invention which provides a method of performing and shifting out the results of a memory built-in self test (MBIST) from a MBIST controller, comprising the steps of performing an MBIST on a memory, storing the results of the MBIST in a plurality of registers that are connected together to form a loop, with an output of the MBIST controller connected to an output of one of the registers, and serially shifting the MBIST results around the loop of registers and also out of the MBIST controller such that when the MBIST results are completely shifted out of the MBIST controller the registers are returned to a same state as before the shifting of the MBIST results through the registers.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4598401 (1986-07-01), Whelan
patent: 5425035 (1995-06-01), Spencer et al.
Khou Beng Chew
Tan Boon Piaw
Wong Jacques
Advanced Micro Devices , Inc.
Chung Phung M.
LandOfFree
Method and apparatus for looping back a current state to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for looping back a current state to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for looping back a current state to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3020557