Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-04-15
2000-04-18
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714724, G01R 3128
Patent
active
060528117
ABSTRACT:
A method and apparatus for locating a critical speed path in an integrated circuit. The apparatus comprises a plurality of controllable clock drivers each coupled to a circuit block of the integrated circuit. The apparatus also comprises a plurality of clocked storage devices each coupled to one of the controllable clock drivers and including a clock input, a data input and a data output. Test circuitry that operates with joint test action group (JTAG) compatible protocol is coupled to the plurality of clocked storage devices and generates a signal that controls the plurality of controllable clock drivers.
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Cady Albert De
Chase Shelly A
Intel Corporation
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