Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-09-23
2003-03-11
Decady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06532557
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to testing the accuracy of integrated circuits; more particularly, the present invention relates to increasing test coverage for integrated circuit systems.
BACKGROUND
As the technology for manufacturing integrated circuits advances, increasingly more logic functions may be included in a single integrated circuit device. Modem integrated circuit (IC) devices include over 100,000 gates on a single semiconductor chip, with these gates interconnected so as to perform multiple and complex functions, such as, for example, those in a graphics controller (or processor). The manufacture of such circuits incorporating such Very Large Scale Integration (VLSI) requires that the fabrication of the circuit be error free, as manufacturing defects may prevent the IC from performing all of the functions that it is designed to perform. Thus, verification of the circuit design, as well as various types of electrical testing, is required after manufacture.
In an IC test system, a test signal pattern called a test vector is provided to an IC device under test conditions and a resultant output from the semiconductor device is compared with an expected signal established in advance to determined whether the semiconductor device under test works correctly or not. A test vector describes the desired test input (or signals), associated clock pulse (or pulses), and expected test output (or signals) for every IC package pin during a period of time, often in an attempt to “test” a particular gate (or macro). For complex circuitry, however, this may involve a large number of test vectors and accordingly a long test time.
As the complexity of all IC increases, so does the cost and difficulty of verifying and electrically testing each of the devices in the IC. From an electrical test standpoint, in order to totally verify that each gate in a VLSI circuit functions properly, test coverage must be performed on each of the gates not only individually (in the digital sense, determining that it is neither stuck-open nor stuck-closed), but also in conjunction with the other gates in the circuit in all possible combinations of operations. This is normally accomplished by automated testing equipment (ATE) that employs test vectors to perform the desired tests.
FIG. 1
is a block diagram of an exemplary IC test system. The IC system includes two functional unit blocks (FUB
1
and FUB
2
) within an IC, each coupled to an input pad and an output pad. Before testing the IC, separate test vectors must be created for each FUB in the IC. The test vector generated for FUB
1
is transmitted to FUB
1
via the input pad. The logic gates within FUB
1
are manipulated according to the content of the test vector. Afterwards, output signals that correspond with the transactions carried out inside the FUB
1
are transmitted to the output pad. Finally, the output signals are compared with an expected test outcome. Subsequently, the same process is carried out for FUB
2
.
One problem with exemplary IC test systems is that the actual input signals within a FUB cannot be directly monitored; only the results of the execution of the signals may be observed. For example, the output of a counter within a FUB may be viewed at the output pad. However, the individual pulses generated by the counter may not be monitored. Therefore, there is no way to verify that the output of the counter is activated under the designed conditions. In addition, a lot of time may elapse between the inputting of a test vector into an FUB and the resulting output to propagate to the output pad. For instance, it may be necessary to wait thousands of clock cycles in order to observe output signals after a test vector has been fed to a FUB. Further, test vectors must be repeatedly loaded for each FUB within an IC. As described above, FUB
1
must be completely tested before a test vector may be loaded to test FUB
2
.
Yet another problem with exemplary IC test systems is that specific circuit configurations within a FUB may have some of its gates inaccessible for all but a special combination of signals, thereby hiding a fault unless a very specific pattern of signals is presented. However, the cost of test that covers 100% of an IC using exemplary IC test methods is very expensive. The excessive expense is due to the high cost of test equipment required to exercise each circuit in the IC. In addition, a lot of time is necessary in order to create the requisite test vectors to test the IC. Further, it is very time-consuming to execute a test vector that examines each possible combination to each gate in the IC. Consequently, integrated circuit manufacturers must currently test less than all of the active devices in an IC, resulting in quality levels of the product being less than optimal. Therefore, a method and apparatus for improving fault coverage and reducing the time to execute a system IC test is desired.
SUMMARY OF THE INVENTION
An integrated circuit is disclosed that includes an output pad, a first functional unit block (FUB) coupled to the output pad and a control circuit coupled to the first FUB. According to one embodiment, the control circuit is adaptable to select a first group or a second group of internal signals within the first FUB that are to be transmitted to the output pad upon initiating a test mode at the integrated circuit. According to a further embodiment, the control circuit is further adaptable to receive a test vector including data that determines whether the first or second group of internal signals are transmitted to the output pad.
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Hurlow Philip
Wong Mark
Blakely , Sokoloff, Taylor & Zafman LLP
De'cady Albert
Lamarre Guy
Silicon Motion Inc.
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