Method and apparatus for improving timing accuracy of a semicond

Details Method and apparatus for improving timing accuracy of a semicond Method and apparatus for improving timing accuracy of a semicond

1996-09-23

1999-08-03

Chung, Phung M.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

H04B 1700

Patent

active

059319623

ABSTRACT:
A semiconductor testing system that performs real-time adjustment of programmed values for test signals using an interface between a system controller and the pin resources. The interface includes a calibration memory that contains timing offset values and amplitude level offset and gain values. An arithmetic logic unit combines these compensation values with the programmed values. The compensated values are then sent to test system registers that control pin resources, such as pin electronics of the semiconductor testing system.

REFERENCES:
patent: 4383218 (1983-05-01), Hansen et al.
patent: 5491649 (1996-02-01), Friday, Jr. et al.

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