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Selected: P

Performance monitoring circuitry for integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Performance monitoring system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Performing memory built-in-self-test (MBIST)

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Peripheral connector with boundary-scan test function

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Peripheral partitioning and tree decomposition for partial scan

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Peripheral partitioning and tree decomposition for partial scan

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Peripheral partitioning and tree decomposition for partial scan

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Permanent failure monitoring in complex systems

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Phase shifter with reduced linear dependency

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Phase shifter with reduced linear dependency

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Physical packaging position information processing system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pin coupler for an integrated circuit tester

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pipeline circuit with a test circuit with small circuit scale an

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pipeline of additional storage elements to shift...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Pipelined data processor with deterministic signature...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Platform ASIC reliability

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Plesiochronous transmit pin with synchronous mode for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Position independent testing of circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Position independent testing of circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Position independent testing of circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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