Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-04-13
2010-10-26
Tabone, Jr., John J (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000, C714S733000, C714S741000, C714S742000, C716S030000
Reexamination Certificate
active
07823034
ABSTRACT:
An electronic device includes a scan-based circuit that includes a combinational decompressor, a combinational compressor, scan chains, and logic which typically includes a number of storage elements. Cycle time normally needed to shift data into or out of a scan cell to/from an external interface of the electronic device is reduced by use of one or more additional storage element(s) located between the external interface and one of the combinational elements (decompressor/compressor). The one or more additional storage element(s) form a pipeline that shifts compressed data in stages, across small portions of an otherwise long path between the external interface and one of the combinational elements. Staged shifting causes the limit on cycle time to drop to the longest time required to traverse a stage of the pipeline. The reduced cycle time in turn enables a corresponding increase in shift frequency.
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Neuveux Frederic J
Waicukauski John A
Wohl Peter
Bever Hoffman & Harms LLP
Harms Jeanette S.
Synopsys Inc.
Tabone, Jr. John J
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