Peripheral partitioning and tree decomposition for partial scan

Details Peripheral partitioning and tree decomposition for partial scan Peripheral partitioning and tree decomposition for partial scan

1997-12-19

2000-10-17

Chung, Phung M.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714724, G01R 3128

Patent

active

06134687&

ABSTRACT:
A method, system and a computer product for a new partial scan technique that incurs significantly less overhead than the full-scan technique and yet achieves very high test coverage in short CPU times are provided. Scan memory elements are selected so that the scanned circuit satisfies two key properties in the test mode. First, the scanned circuit has partitions that are peripherally interacting finite state machines (peripheral partitions). Second, the memory element dependency graph (S-graph) of each peripheral partition of the scanned circuit has a tree structure. An efficient for algorithm peripheral partitioning and tree decomposition is provided. The scan memory element selection algorithm iteratively partitions the S-graph into disjoint sub-graphs with the tree structure.

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