Platform ASIC reliability

Details Platform ASIC reliability Platform ASIC reliability

2007-08-07

2007-08-07

Tu, Christine T. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C716S030000, C324S522000

Reexamination Certificate

active

11287927

ABSTRACT:
A method for monitoring a fabrication of a circuit is disclosed. The method generally includes a step of (A) fabricating a chip only up to and including a first metal layer such that (i) a core region of the chip may has an array of cells, (ii) each of the cells may have a plurality of transistors and (iii) the chip may include a plurality of flip-flops. After the fabricating of step A has started, another step may be (B) designing a plurality of upper metal layers above the first metal layer. The upper metal layers (i) may interconnect a plurality of the cells to form the circuit, (ii) may form a plurality of scan chains from a number of the flip-flops not used in the circuit and (iii) may form a plurality of paths in the upper metal layers. Each of the paths generally connects a respective output of a first of the scan chains to a respective input of a second of the scan chains. Further steps may include (C) fabricating the chip to add the upper metal layers and (D) measuring a transition delay along each of the paths to characterize the fabrication of the circuit.

REFERENCES:
patent: 6157210 (2000-12-01), Zaveri et al.
patent: 6897678 (2005-05-01), Zaveri et al.
patent: 6990643 (2006-01-01), McBride

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