Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-07-26
2009-12-01
Ellis, Kevin L (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C365S201000, C324S765010, C714S731000
Reexamination Certificate
active
07627795
ABSTRACT:
A pipelined data processing system includes functional circuitry having a plurality of test points located at predetermined circuit nodes within the functional circuitry, at least one staging storage element associated with a pipeline stage of the data processing system which is coupled to receive test data directly from the plurality of test points, and a multiple input shift register (MISR) coupled to receive test data from the at least one staging storage element and provide a MISR result. In one aspect, the at least on staging storage element has a plurality of staging storage elements wherein each of the plurality of staging storage elements corresponds to a different pipeline stage of the data processing system. In another aspect the MISR result is independent of varying memory access times.
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U.S. Appl. No. 11/355,681, filed Feb. 16, 2006.
Gumulja Jimmy
Moyer William C.
Chiu Joanne G.
Ellis Kevin L
Freescale Semiconductor, Inc
King Robert L.
Merant Guerrier
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