Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-06-19
2000-06-06
Chung, Phung M.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714724, G06F 1100
Patent
active
060732652
ABSTRACT:
A pipeline circuit with a test circuit in small circuit scale includes a pipeline circuit including a plurality of groups of flipflops arranged in series and a plurality of combinational circuits respectively arranged between the plurality of groups of flipflops and each having an input connected to an output of a group of flipflops at a previous stage and an output connected to a group of flipflops at a subsequent stage. The plurality of groups of flipflops include groups of flipflops subjected to scan conversion and groups of flipflops not subjected to scan conversion. The pipeline circuit, with a test circuit also includes a scan chain interconnecting the groups of flipflops subjected to scan conversion. An automatic test pattern generating method for testing the pipeline circuit with a test circuit, is also claimed.
REFERENCES:
patent: 5640403 (1997-06-01), Ishiyama et al.
patent: 5668481 (1997-09-01), Sheu et al.
patent: 5930271 (1999-07-01), Takahashi
patent: 6014763 (2000-01-01), Dhong et al.
Chung Phung M.
Mitsubishi Denki & Kabushiki Kaisha
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