Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-10-18
2010-02-02
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000
Reexamination Certificate
active
07657804
ABSTRACT:
A method and apparatus for conveying test response data from an integrated circuit to ATE via a plesiochronous interconnect. The integrated circuit includes a core logic unit and a first transmitter coupled thereto by a first data path. In a normal mode, data conveyed from the core logic unit to the transmitter may be transmitted plesiochronously over an interconnect coupled to the transmitter output. The integrated circuit further includes a second data path coupled between the core logic unit and the interconnect. During a test mode, test response data may be conveyed from the core logic unit to ATE via the second data path and the interconnect, wherein the test response data is synchronously transmitted over the interconnect.
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Kowert Robert C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Sun Microsystems Inc.
Ton David
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