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Method for performing testing of a simulated storage device...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method for powering-up a microprocessor under debugger control

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method for programming and/or testing for correct...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method for providing bitwise constraints for test generation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method for providing bitwise constraints for test generation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method for providing user definable algorithms in memory BIST

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method for quality and reliability assurance testing of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method for race prevention and a device having race...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method for reducing switching activity during a scan...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method for remotely testing microelectronic device over the...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method for scan controlled sequential sampling of analog...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method for scan testing and clocking dynamic domino circuits...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method for scan testing of digital circuit, digital circuit...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method for segmenting BIST functionality in an embedded...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method for selecting operation cycles of a semiconductor IC for

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method for self-testing integrated circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method for separating shift and scan paths on scan-only,...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method for state-based oriented testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Method for supervising parallel processes

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method for testing a circuit unit to be tested and test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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