Method for reducing switching activity during a scan...

Details Method for reducing switching activity during a scan... Method for reducing switching activity during a scan...

2006-01-10

2006-01-10

Torres, Joseph D. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S728000, C714S729000

Reexamination Certificate

active

06986090

ABSTRACT:
A method for reducing the switching activity during both scan-in and scan-out operations of an integrated circuit with reduced detrimental effect on test pattern effectiveness and test time is described. The method makes use of a sample set of patterns to determine the probabilities of same and opposite relationships between stimulus and result values, and uses these probabilities to determine memory element pair compatibilities. Scan chains are ordered preferentially by connecting adjacently compatible memory elements, and inversions are inserted between selected memory element pairs based on those probabilities. Unspecified stimulus bits are filled in to reduce the switching activity based on the scan chain ordering and inversions.

REFERENCES:
patent: 6529861 (2003-03-01), Patra et al.
J. Monteiro, S. Devadas, and B. Lin, “A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits,” Proc. 31st Design Automation Conf., pp. 12-17, 1994.
Seiji Kajihara, Kohei Miyase: On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits. ICCAD 2001: 364-369.
S. T. Chakradhar, A. Balakrishnan, and V. D. Agrawal, “An exact algorithm for selecting partial scan flip-flops”, Design Automation Conference, pp. 81-86, 1994.

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