Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1996-11-15
1999-08-10
Palys, Joseph E.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714 30, G01R 3128
Patent
active
059352663
ABSTRACT:
A method and apparatus are disclosed for powering-up a microprocessor in a system under debugger control. The microprocessor comprises I/O connection pins, internal logic, and a reset condition responsive to a reset signal. Additionally, the microprocessor has a boundary scan architecture, such as an IEEE 1149.1 (JTAG) compliant interface, which includes a boundary scan register (BSR) and at least one design-specific test data register. The BSR has normal and test modes. In the normal mode, the BSR operatively connects the internal logic to the I/O connection pins. In the test mode, the BSR operatively isolates the internal logic from the I/O connection pins. The method comprising first detecting when power is applied to the microprocessor. Once power is detected and while the microprocessor remains in the reset condition, the BSR is put into tile test mode to isolate the internal logic from the I/O connection pins. Next, the debugger controls the microprocessor via the data register of the JTAG interface, conducting the necessary functions pursuant to power-up. Once the power-up functions are performed and the reset signal is disasserted, the internal logic can be reconnected with the I/O connection pins by returning the BSR to its normal mode.
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Thurnhofer Stefan
Whalen Shaun P.
Iqbal Nadeem
Lucent Technologies - Inc.
Palys Joseph E.
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