Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2004-12-20
2009-11-03
Ellis, Kevin L (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S735000
Reexamination Certificate
active
07613973
ABSTRACT:
A method for enabling bitwise or bit slice constraints to be provided as part of the test generation process, by providing a language structure which enables these constraints to be expressed in a test generation language such as e code for example. The language structure for such bitwise constraints is then handled in a more flexible manner, such that the test generation process does not attempt to rigidly “solve” the expression containing the constraint as a function. Therefore, the propagation of constraints in such a structure do not necessarily need to be propagated from left to right, but instead are generated in a multi-directional manner. The language structure is particularly suitable for such operators as “[: ]”, “|”, “&”, “^”, “˜”, “>>” and “<<”.
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Baruch Guy
Lagoon Vitaly
Cadence Design (Israel) II Ltd.
Ellis Kevin L
Gandhi Dipakkumar
Rosenberg , Klein & Lee
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