Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-05-10
2011-05-10
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S735000
Reexamination Certificate
active
07941716
ABSTRACT:
A method for race prevention includes: selectively providing data or scan data to a input latching logic, activating the input latching logic for a first scan mode activation period, introducing a substantial time shift between the first scan mode activation period and a second scan mode activation period, and activating a output latching logic, connected to the input latching logic for a second scan mode activation period. A device having race prevention capabilities includes: an interface logic, a input latching logic, a output latching logic and a control logic. The interface logic is adapted to selectively provide data or scan data to the input latching logic. The control logic is adapted to introduce a substantial time difference between an end point of a first scan mode activation period of the input latching logic and a start point of a second scan mode activation period of the output latching logic.
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Kuzmin Dan
Priel Michael
Rozen Anton
Britt Cynthia
Freescale Semiconductor Inc.
Gandhi Dipakkumar
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