Method for supervising parallel processes

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C714S011000, C714S012000, C714S013000, C714S045000, C714S819000, C714S820000

Reexamination Certificate

active

06880119

ABSTRACT:
The present invention relates to a method of supervising parallel processors in a data system that comprises a first system CP-A and a second system CP-B. The method comprises the steps of:generating a first status word STWA in the first system CP-A and a parallel second status word STWB in the second system CP-B;generating in the first system CP-A a first check code CCA from the first status word STWA;generating in the second system CP-B a second check code CCB from the second status word STWB;sending the first check code CCA from the first system CP-A to the second system CP-B; andrecreating the first data word STWA in the second system CP-B by evaluating the first check code CCA, the second check code CCB and the second data word STWB.

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