Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-01-25
2004-02-10
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000, C714S726000, C324S763010
Reexamination Certificate
active
06691269
ABSTRACT:
The present invention relates generally to testing of integrated circuits and, more specifically, to a method for performing fast sequential access of circuit nodes and a circuit for use therewith.
BACKGROUND OF THE INVENTION
As the density of circuit boards containing integrated circuits (ICs) increases, it becomes more difficult to access the board signal wires using metal probes, or a “bed of nails”. This has led to the development by members of the Institute of Electrical and Electronic Engineers (IEEE) of two test standards for circuit board testing. The standard for accessing digital signals of integrated circuit (IC) pins is denoted 1149.1 and was first published in 1990. An extension to the 1149.1 standard that is aimed at accessing analog signals is denoted 1149.4 and was first published Mar. 28, 2000, though preliminary drafts of the standard were available to many people prior to that date.
The 1149.4 standard will be better understood by reference to
FIG. 1
which illustrates general architecture of an IC
10
which contains 1149.4 test access circuitry. The 1149.4 standard extends the 1149.1 digital test access port (TAP)
12
by adding two analog test bus pins
14
and
16
, denoted AT1 and AT2, to allow the signal at any function pin of an IC to be accessed via these two pins. To monitor the voltage at a function pin
18
via an analog test bus pin
16
, two switches are enabled. As shown in
FIG. 2
, which illustrates an analog boundary module (ABM)
20
, one switch
22
(or
24
) for function pin
18
, and one (not shown) in a test bus interface circuit (TBIC)
26
for the IC. Common signals generated by the TAP to control all ABMs may include ShiftDR
30
, ClockDR
32
, UpdateDR
34
, and one or more Mode signals
36
and
38
. To enable the two switches, appropriate logic bits are shifted serially, or “scanned”, through a boundary scan register (BSR) linked by wires following the path of dashed line
40
, such that a scan register update latch
42
(or
44
) controlling each switch is loaded with the logic bits. The boundary scan shift register has N bits, where N is any non-zero integer, and hence N or more clock cycles are required to shift in bits to all of the boundary scan shift register elements (or stages).
Each time a function pin signal is to be accessed, it is necessary to perform at least the sequence of steps described below (where “toggle” means “generate a rising and falling edge on”), according to the 1149.1/1149.4 TAP controller state diagram shown in
FIG. 3
(and in the waveforms of FIG.
7
). The numerals 1 or 0 adjacent the states are prescribed values of the TMS input to the TAP.
The sequence of steps are: 1. while TMS=1, toggle TCK to proceed from Run-test/Idle state
50
, Update-DR state
52
or Update-IR state
54
to Select-DR-Scan state
56
; 2. while TMS=0, toggle TCK to proceed from Select-DR-Scan state
56
to Capture-DR state
58
, in which new data overwrites the BSR contents via multiplexer
60
(
FIG. 2
) and other multiplexers; 3. while TMS=0, toggle TCK to proceed from Capture-DR state
58
to Shift-DR state
62
; 4. while TMS=0, repeatedly toggle TCK to scan in N bits to completely fill the BSR shift register elements
64
,
66
,
68
and
70
, in
FIG. 2
; 5. while TMS=1, toggle TCK to proceed from Shift-DR state
62
to Exit1-DR state
72
; and 6. while TMS=1, toggle TCK to proceed from Exit1-DR state
72
to Update-DR state
52
, which updates all update latches
42
,
44
,
74
and
76
, in
FIG. 2
to output new bit values.
The minimum number of TCK clock cycles to select a different analog switch to be enabled is therefore N
TCK
=4+N. The number of boundary scan shift register bits per ABM, as required by 1149.4, is four (elements
64
,
66
,
68
,
70
, in FIG.
2
). Four shift register bits are also required in the TBIC
26
. Some of the pins of the IC may be digital, and hence may not have an associated ABM—these pins may have only one boundary scan bit per pin and still be compatible with 1149.4 and 1149.1. Although 1149.4 is intended to provide analog access to analog pins, it can also be used to provide analog access to digital pins as suggested by S. Sunter in “Cost/benefit analysis of the P1149.4 mixed-signal test bus” in
IEE Proceedings, Circuits, Devices, and Systems
, December 1996, on pages 394 and 395. This allows a tester to measure the DC characteristics of all pins of an IC via the TAP and analog bus pins, thus greatly reducing the number of probes needed to probe ICs on a wafer and the number of channels needed in a tester. To enable this simplification in test equipment, every pin must have an ABM. Therefore, for an IC with P pins, N=4P+4 bits would be needed. For P>100, N is approximately equal to 4P.
Clock frequencies for TCK, when testing a stand-alone IC, typically range from f
TCK
=1 MHz to f
TCK
=50 MHz. The time to scan in N bits is N
TCK
/f
TCK
. If the time to measure each pin's voltage is T
Measure
, the total time per pin measurement is T
Measure
+N
TCK
/f
TCK
. The time to measure the voltage at P pins is therefore:
P
(
T
Measure
+N
TCK
/f
TCK
)=
P
(
T
Measure
+4
P/f
TCK
)=
PT
Measure
+4
P
2
/f
TCK
)
which is proportional to the square of the number of pins.
To measure the standard DC characteristics of a pin, six voltages must be measured, corresponding to: output drive low (IOL), output drive high (IOH), input leakage low (IIL), input leakage high (IIH), maximum input voltage for a logic 0 (VIL) and minimum input voltage for logic 1 (VIH). Therefore the total time to measure/apply 6 voltages for an IC with P pins is:
6
P
(
T
Measure
+4
P/f
TCK
)=6
PT
Measure
+24
P
2
/f
TCK
For an IC with 100 signal pins, f
TCK
=10 MHz, and T
Measure
=10 &mgr;s, the test time would be approximately 27 ms, and the number of test vectors would be 270,000. For an IC with 1000 signal pins and F
TCK
=10 MHz, the test time would be approximately 2.7 seconds, and the number of test vectors would be 27,000,000. The test time for a conventional tester having parallel access to all signal pins of the IC, and having a parametric measurement unit per pin, is typically 20 ms, regardless of the number of pins, and the number of vectors would be typically fewer than a few thousand.
There is a need for a method and circuit architecture which reduces the circuit node access time via an analog bus from the prior art method that is proportional to the square of the number of pins on the IC.
SUMMARY OF THE INVENTION
The present invention seeks to provide a circuit node sequential access method, and an IEEE 1149.4 compatible circuit for use therewith, in which the time to access a plurality of nodes is linearly proportional to the number of nodes accessed.
The present invention provides a method in which, after the BSRs have been initialized in the manner explained earlier to access the first of a plurality of circuit nodes, the number of clock cycles required to access subsequent circuit nodes may be reduced by simply shifting the switch enabling bit from one BSR to the next while preventing the TAP controller from altering the shifted boundary module bit values during the Capture-DR state and altering the state of other analog switches and/or signal node drivers during the UpdateDR state. This may be achieved by suppressing the capture operation when the TAP controller is sequenced through the Capture-DR state.
The method of the present invention is generally defined as a method for sequentially accessing circuit nodes in an IEEE 1149.4 compatible mixed-signal circuit having a TAP controller, a boundary scan register having boundary modules associated with each circuit node, analog busses for accessing the circuit nodes and connecting analog pins and each boundary module, the boundary modules including an analog boundary module having analog switches for selectively accessing the busses, the boundary register including shift register elements and associated up
Dildine R. Stephen
LogicVision, Inc.
Proulx Eugene E.
LandOfFree
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