Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-07-10
2007-07-10
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
10604908
ABSTRACT:
A method and circuit design for enabling both shift path and scan path functionality with a single port LSSD latch designed for scan path functionality only, without increasing the device's internal real estate and without substantial increase in overall device real estate. The circuit design eliminates the need for additional logic components to be built into the internal circuitry of the device and also eliminates the cost of providing dual port LSSD latches within the device. Implementation of the invention involves providing a unique configuration of low level logic components as input circuitry that is coupled to a pair of single port LSSD latches that operate as the input latches for the device. The low level logic components accomplishes the splitting of scan chain inputs and shift chain inputs to the input latches and thus enables the single ported LSSD latches to operate with similar functionality as dual ported LSSD latches.
REFERENCES:
patent: 4066882 (1978-01-01), Esposito
patent: 6639848 (2003-10-01), Maejima
Multiplexers (Wayback Machine Archive: http://www.cs.umd.edu/class/spring2003/cmsc311/Notes/Comb/mux.html , Published on Jul. 8, 2003).
Anand Darren L.
Barth, Jr. John E.
Oakland Steven F.
Ouellette Michael R.
Dillon & Yudell LLP
International Business Machines - Corporation
Lamarre Guy
Le Strange Michael J.
Radosevich Steven D.
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