Method for testing a circuit unit to be tested and test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S718000, C365S201000

Reexamination Certificate

active

07039838

ABSTRACT:
The invention provides a method for testing a circuit unit (101) to be tested, in which a test time is reduced, at least one word line (102a–102N) of the circuit unit (101) to be tested being activated by application of at least one test signal (103) to the word line (102a–102N), the at least one word line (102a–102N) being deactivated by removal of the test signal (103) from the word line (102a–102N), the word lines among all the word lines (102a–102N) which have not run through an activation-deactivation cycle being read out in order to determine an influence of the activation and deactivation, and the test result being output.

REFERENCES:
patent: 5305253 (1994-04-01), Ward
patent: 5499213 (1996-03-01), Niimi et al.
patent: 5959930 (1999-09-01), Sakurai
patent: 6023440 (2000-02-01), Kotani et al.
patent: 6038181 (2000-03-01), Braceras et al.
patent: 6067261 (2000-05-01), Vogelsang et al.
patent: 6191985 (2001-02-01), Grätz et al.
patent: 6295238 (2001-09-01), Tanizaki et al.
patent: 2002/0066058 (2002-05-01), Sugamoto et al.
IBM, Multiple Word Line Selection for Reducing Semiconductor Memory Test Time., Oct. 1990, IBM Technical Disclosure Bulletin, vol. 33, Issue 5, pp. 447-448, NN9010447.

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