Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-05-02
2006-05-02
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000, C365S201000
Reexamination Certificate
active
07039838
ABSTRACT:
The invention provides a method for testing a circuit unit (101) to be tested, in which a test time is reduced, at least one word line (102a–102N) of the circuit unit (101) to be tested being activated by application of at least one test signal (103) to the word line (102a–102N), the at least one word line (102a–102N) being deactivated by removal of the test signal (103) from the word line (102a–102N), the word lines among all the word lines (102a–102N) which have not run through an activation-deactivation cycle being read out in order to determine an influence of the activation and deactivation, and the test result being output.
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IBM, Multiple Word Line Selection for Reducing Semiconductor Memory Test Time., Oct. 1990, IBM Technical Disclosure Bulletin, vol. 33, Issue 5, pp. 447-448, NN9010447.
Proell Manfred
Van Der Zanden Koen
De'cady Albert
Fish & Richardson P.C.
Tabone, Jr. John J.
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