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Integrated circuit with tap controller

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuit with test circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Integrated circuit with test signal routing module

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Integrated circuit, test system and method for reading out...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated circuits carrying intellectual property cores and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated data download

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated device with an improved BIST circuit for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated device with operativity testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated electronic module with hardware error infeed for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated excitation/extraction system for test and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated module having a plurality of separate substrates

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated multi-channel analog test instrument architecture...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Integrated system logic and ABIST data compression for an...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated test apparatus and method therefor

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated test circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated test circuit, a test circuit, and a test method...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Integrated test-on-chip system and method and apparatus for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integrated testing of serializer/deserializer in FPGA

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integration of embedded and test mode timer

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Integration type input circuit and method of testing it

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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