Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-10-19
2002-03-26
DeCady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06363507
ABSTRACT:
This invention relates generally to automatic test equipment, and more specifically to a test instrument architecture for testing analog and mixed-signal electronic circuit assemblies.
Electronic circuit assemblies are typically tested at least once during their manufacture. One type of test is commonly known as functional testing, which is typically used to determine whether a unit under test (UUT) is capable of performing properly in its final operating environment. To this end, functional testing includes applying test stimuli to the UUT, observing responses generated by the UUT, and then determining whether the observed responses are acceptable for a properly functioning UUT.
Functional testing of circuit assemblies that include just analog or both analog and digital (i.e., mixed-signal) circuitry poses particular problems because the applied test stimuli and observed responses for these assemblies normally include many different waveforms and levels. Further, the observed responses must usually be evaluated relative to the test stimuli and sometimes each other. It is therefore often very challenging to generate the test stimuli and evaluate the responses in a way that closely simulates the final operating environments of these circuit assemblies.
Further, because functional testing of circuit assemblies typically occurs in a manufacturing environment, it is important that circuit assemblies are tested quickly and that problems in the assemblies are quickly identified, thereby keeping manufacturing costs down.
FIG. 1
shows conventional test equipment architecture
100
that may be used to perform functional testing of electronic circuit assemblies with analog and/or mixed-signal circuitry. Architecture
100
includes a number of discrete instruments
104
,
106
, and
108
, which apply test stimuli to a UUT
112
and observe responses generated by the UUT
112
.
Because the UUT
112
may include analog or mixed-signal circuitry, the instruments
104
,
106
, and
108
may include both analog and digital instruments. For example, the analog instruments may include a function generator for generating arbitrary waveforms or standard waveforms such as sine waves, triangle waves, or square waves; a multi-meter for measuring levels generated by the UUT
112
; a waveform digitizer for sampling waveforms generated by the UUT
112
and storing the samples in memory (not shown) for subsequent analysis; or a timer/counter for making frequency, period, and time interval measurements.
In addition, the digital instruments may include devices for driving digital signals and sensing logic states on the UUT
112
, and for measuring certain parameters of digital signals produced by the UUT
112
. For example, one of the digital instruments may be used to measure logic levels of a digital signal at particular points in time.
The instruments
104
,
106
, and
108
are controlled by a host computer
102
, which communicates with the instruments
104
,
106
, and
108
via a buss
114
. The instruments
104
,
106
, and
108
are also normally connected to a buss
116
, which carries triggering signals between the instruments. In a typical test configuration, the busses
114
and
116
are compatible with a standard interface such as HP-IB (IEEE-488) or VXIbus (IEEE-1155). Accordingly, the host computer
102
can be programmed to synchronize and control the operation of the instruments
104
,
106
, and
108
by specifying control and triggering signals carried by the busses
114
and
116
, respectively.
As mentioned above, functional testing includes applying test stimuli to a UUT and observing responses generated by the UUT. For this reason, typical architecture
100
also includes a switch matrix
110
, which is also controlled by the host computer
102
via the buss
114
. The switch matrix
110
typically includes relays that are controlled to connect the instruments
104
,
106
, and
108
to selected nodes of the UUT
112
. Nodes selected during functional testing are typically those nodes that are used in the final operating environment of the UUT.
For example, one or more of the instruments
104
,
106
, and
108
may be connected to nodes of the UUT
112
for applying test signals to the nodes. Further, response signals at other nodes of the UUT
112
may be measured by one or more of the instruments
104
,
106
, and
108
. Accordingly, the host computer
102
may be programmed to actuate the relays in the switch matrix
110
, thereby making necessary connections between the instruments
104
,
106
, and
108
and the nodes of the UUT
112
during a test session.
An example of architecture
100
, in which both analog and digital instruments are connected to a UUT via a switch matrix, is illustrated in U.S. Pat. No. 4,070,565 assigned to TERADYNE®, Inc., Walnut Creek, Calif., USA. Another example of test equipment architecture, in which driver instruments are connected directly to a UUT while measurement instruments are connected to the UUT through a switch matrix, is illustrated in U.S. Pat. No. 4,216,539, which is also assigned to TERADYNE®, Inc.
Although test equipment architecture
100
has been used to perform functional testing of electronic circuit assemblies, we have recognized several shortcomings. For example, it was mentioned above that functional testing is typically used to determine whether a UUT can perform properly in its final operating environment. This generally means that architecture
100
must simulate the operating environment of the UUT as closely as possible and accurately evaluate the performance of the UUT in this simulated environment. However, conventional architecture
100
is based upon a collection of discrete instruments
104
,
106
, and
108
, which frequently cannot simulate the operating environment as desired.
For example, if multiple measurements were needed to evaluate a signal at a node of a UUT, then the host computer
102
might control the switch matrix
110
to connect multiple measurement instruments to that node. However, this might subject the node to an unwanted loading condition that would generally not occur during normal operation.
Even if connecting multiple measurement instruments to a node did not result in an unwanted loading condition, the accuracy of the measurements may still be affected. In particular, different measurement instruments may have different input configurations, each with its own inherent delay characteristics. These delays may be unknown and variable and may even add up across conventional architecture
100
, thereby further decreasing the accuracy of measurements.
Instead of connecting multiple measurement instruments to a single node, the host computer
102
may alternatively control the switch matrix
110
to connect the measurement instruments to a node in a sequential manner. Although this approach would probably avoid an unwanted loading condition, it would generally require that multiple measurements at a node be made at different times. This would preclude simultaneous measurements at the node and make it very difficult to analyze one measurement relative to another with any level of accuracy or repeatability.
Another shortcoming of conventional architecture
100
is that it is generally asynchronous. Again, this is because architecture
100
is built around a collection of discrete instruments
104
,
106
, and
108
. Although the instruments
104
,
106
, and
108
are connected to the triggering buss
116
and can therefore be made to respond to the same triggering events, the instruments
104
,
106
, and
108
do not typically operate in conjunction with the same clock reference. This makes it very difficult to predict when the instruments will actually respond to the triggering events. Consequently, it may be difficult to achieve good correlation between measurements made by different instruments.
Still another shortcoming of having an architecture based upon a collection of discrete instruments
104
,
106
, and
108
is that there is frequently a duplication of functions, thereby increasing
Arena John J.
Chen Jiann-Neng
Davis Richard P.
Lind David J.
Lopes Teresa P.
DeCady Albert
Lamarre Guy
Teradyne Legal Dept.
Teradyne, Inc.
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