Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-05-24
2005-05-24
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C327S433000, C327S437000, C327S484000, C326S031000, C326S121000
Reexamination Certificate
active
06898745
ABSTRACT:
An integrated device having a pad receiving, in a standard operative condition, an input signal having a first value and, in a test operative condition, a test voltage having a second value higher than the first value; an input stage connected to the pad and including an electronic component having a first terminal connected to the pad; a third-level detecting stage connected to the pad and supplying a logic third-level signal having a first level in presence of the input signal and a second level in presence of the test voltage; and a selector connected to a second terminal of the electronic component and structured to connect the second terminal to a reference potential in the presence of the first logic level of the third-level signal and to a biasing voltage higher than the reference potential and lower than the second value in the presence of the second logic level of the third-level signal.
REFERENCES:
patent: 5057715 (1991-10-01), Larsen et al.
patent: 5789951 (1998-08-01), Shen et al.
patent: 6157224 (2000-12-01), Linder
Branchetti Maurizio
Mulatti Jacopo
Picca Massimiliano
Zanardi Stefano
Lamarre Guy J.
Tarleton E. Russell
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