Integrated test circuit, a test circuit, and a test method...

Details Integrated test circuit, a test circuit, and a test method... Integrated test circuit, a test circuit, and a test method...

2007-12-18

2007-12-18

Kerveros, James C. (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S716000

Reexamination Certificate

active

10766038

ABSTRACT:
A macro block MB2including a physical-layer circuit PHY for communications performs transmission and reception processing to and from a macro block MB1at a clock frequency CF1. A test circuit TC includes a test transmission buffer TXB that stores a transmission data signal from a test input terminal TPI at a frequency CF2that is lower than the frequency CF1, and a test reception buffer RXB that outputs a reception data signal to a test output terminal TPO at a frequency CF3that is lower than the frequency CF1. After the transmission buffer TXB has stored the transmission data signal from the terminal TPI at the frequency CF2, it outputs the stored transmission data signal to the MB2at the frequency CF1. After the reception buffer RXB has stored the reception data signal from the MB2at the frequency CF1, it outputs the stored reception data signal to the terminal TPO at the frequency CF3.

REFERENCES:
patent: 5787114 (1998-07-01), Ramamurthy et al.
patent: 5940414 (1999-08-01), Takano et al.
patent: 6286119 (2001-09-01), Wu et al.
patent: 6671839 (2003-12-01), Cote et al.
patent: A 2002-343864 (2002-11-01), None
U.S. Appl. No. 10/765,895, filed Jan. 29, 2004, Nishida et al.

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