Integrated circuit with test circuit

Details Integrated circuit with test circuit Integrated circuit with test circuit

2006-11-21

2006-11-21

Tu, Christine T. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S739000, C714S732000

Reexamination Certificate

active

07139953

ABSTRACT:
Integrated circuit with an application circuit (1) to be tested, and a self-test circuit (5-16) which is provided for testing the application circuit (1) and comprises an arrangement (5-9) for generating desired test patterns which are applied to the application circuit (1) for test purposes, wherein the output signals occurring in dependence upon the test patterns through the application circuit (1) are evaluated by means of a signature register (13), the arrangement (5-9) for generating the desired test patterns comprising a bit modification circuit (9) which individually controls first control inputs of combination logics (6, 7, 8) in such a way that a pseudo-random sequence of test patterns supplied by a shift register is modified such that, by approximation, the desired test patterns are obtained, and which controls second control inputs of the combination logics (6, 7, 8), by means of which the first control inputs can be blocked, such that those test patterns that are supplied by the shift register (5) and are already desired test patterns are not modified by the bit modification circuit (9) by means of controlling the first control inputs of the combination logics (6, 7, 8).

REFERENCES:
patent: 4503537 (1985-03-01), McAnney
patent: 4862068 (1989-08-01), Kawashima et al.
patent: 5762216 (1998-06-01), Takeuchi

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