Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-08-13
2001-07-03
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06256761
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated electronic module which is equipped with at least one hardware error infeed for checking purposes as well as a number of terminals. The present invention also relates to a method for simulating hardware errors on an integrated electronic module which is equipped with at least one hardware error infeed for testing purposes.
2. Description of the Prior Art
For purposes of testing electronic devices, particularly by customers when purchasing from a manufacturer, hardware errors are simulated and the corresponding correct response of the device, among other things, is thereby checked. Interruptions of lines or plug contacts, shorts, inversions, etc., are, therefore, simulated. The test is usually directed to whether and to what extent such an error can be reliably detected, localized, traced to its possible cause and, finally, reported in the device. The simulation of hardware errors in integrated electronic modules (ICs), particularly application-oriented integrated modules (ASICs), turns out to be difficult, if not impossible, to the extent that the internal components and lines of an IC are shut off from direct access.
Until now, error infeeds have been realized through intermediate adapters, switches, jumpers, special assemblies, extra busses and various other methods. A functional hardware error—e.g., inversion of the data or addresses, generation of an interrupt and other similar errors—has been fed in through adjustment of the switch, insertion of the special assembly, and so on. The methods utilized until now presuppose a one-time, expensive development, documentation, production and test of the required equipment, which is utilized only for purchase in the presence of the customer. Furthermore, these methods are not uniform and not standardized. In commissioning, this demands repeated and precise studying by the personnel of the methods applied in each individual system. Also, either one has to be satisfied with generating a relatively low number of errors “by hand” or one has to create a separate means for controlling the error generation which, above all else, results in additional hardware outlay.
It is thus an object of the present invention to develop a hardware error infeed that can be executed both simply and uniformly for different types of ICs and that can keep the required outlay for additional hardware components relatively low.
SUMMARY OF THE INVENTION
This object is achieved in an integrated electronic module of the abovementioned type by means of a module in which the control logic includes at least one terminal as data input for the entering of command signals—this terminal being led out of the module—as well as one error control output connected to a signal input of the error infeed(s). The control logic is arranged to decode the command signals entered via the data input, to derive commands for error control therefrom and to apply error control signals at the at least one error control output corresponding to these commands.
This solution allows a flexible response to hardware errors via the error control logic. The number of terminals reserved for the hardware error infeed can be kept to a limited few, e.g. less than five, even if a large number of hardware error simulations are to be implemented. Furthermore, assemblies which previously had to be attached may now be omitted.
One embodiment of the present invention includes at least one terminal for a clock input of the error control logic. This offers an advantage in that the control logic can be operated independent of the operating function of the integrated module and its temporal sequences.
It is particularly advantageous for the present invention, particularly with reference to the module terminals, if the control logic is constructed as part of a boundary scan test logic of the module, the data input is constructed as test data input of a test interface of the boundary scan test logic, and a command register decoder of the boundary scan test logic is arranged to detect commands for error control and to apply error control signals at the at least one error control output corresponding to these commands. Indeed, this also lowers the hardware outlay requirements.
It is also favorable, in order to be able to actuate a greater number of errors or error combinations in simple fashion, if an error address register is provided in the control logic for selecting one or more error control outputs from a total number of error control outputs.
The present invention further encompasses a method of the abovementioned type by means of a method in which command signals are transmitted to a control logic provided in the module via a data input that is led out of the module, the command signals are decoded in the control logic wherein commands for error control are derived therefrom, and the at least one error infeed is controlled according to these error control commands. It is therein advantageous, e.g. in the simultaneous simulation of a plurality of hardware errors, if different commands are respectively given for the activation and deactivation of the error infeed(s).
In a preferred embodiment of the present invention, which further simplifies the execution of the error simulation, the transmission of the command signals occurs via the test data input of a test interface of the boundary scan test logic, and the decoding of the command signals occurs in a command register decoder of the boundary scan test logic. It is therefore favorable—e.g., in order to control a great number of errors or error combinations in simple fashion—if an error address register is loaded with an error address consequent to a corresponding error control command, and a number of error infeeds are selected and controlled on the basis of this error address in consideration of the initiating error control command.
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Deix Johann
Ghameshlu Majid
Krause Karlheinz
Bell Boyd & Lloyd LLC
Chase Shelly A
De'cady Albert
Siemens Aktiengesellschaft
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