Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-04-24
2007-04-24
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S763000, C714S718000
Reexamination Certificate
active
10413612
ABSTRACT:
ABIST apparatus with integrated directory compare logic functionality, and ABIST error detection functionality. The apparatus includes two subsystems NOR'ed together. The first subsystem is for bit-wise logically ANDing corresponding array valid bits and tag valid inputs, generating “0” for a match and “1” for a mis-match, and logically ORing the bit-wise result to generate a “1” hit if there are any bit-wise mismatches. The second subsystem further receives ABIST control logic as an input to either: (a). combine array valid bits tag valid inputs to produce valid output, or (b) compare array valid bits with tag valid inputs. The apparatus further includes logical NOR functionality for the outputs of the first and second subsystems.
REFERENCES:
patent: 2001/0026483 (2001-10-01), Hasegawa et al.
patent: 2002/0194545 (2002-12-01), Abbott
patent: 2003/0051197 (2003-03-01), Evans
Bunce Paul A.
Davis John D.
Knips Thomas J.
Plass Donald
Augspurger Lynn L.
De'cady Albert
Gandhi Dipakkumar
Goldman Richard M.
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