Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-04-09
2004-06-29
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S040000, C370S241000
Reexamination Certificate
active
06757855
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to data processing systems, and in particular, to the testing of integrated circuit processing devices.
BACKGROUND INFORMATION
The increased performance in modern processing devices (for example, microprocessors and microcontrollers) complicates the testing and verification of the devices during manufacturing. Typically, testing of a microprocessor, or similar complex very large scale integration (VLSI) device is performed in an automatic test equipment (ATE) environment. Commercial test devices include the Teradyne Model J973 VLSI test system (manufactured by Teradyne, Inc., Boston, Mass.), and the IMS Digital Test Station (manufactured by Integrated Management Systems, Inc., Beaverton, Oreg.). However, with increasing processor speeds, and a concommitant increase in bus speeds, full speed testing of a complex VLSI device in an ATE environment becomes increasingly more complicated. Consequently, there is a need in the art for methods and apparatus for testing VLSI devices at full speed.
SUMMARY OF THE INVENTION
The aforementioned needs are addressed by the present invention. Accordingly, there is provided, in a first form, a test interface apparatus. The apparatus includes a first port having a first maximum data rate and at least one second port having a second maximum data rate. A switching unit within the apparatus is operable for transferring data between the first and at least one second ports and a buffer contained therein in response to a first command signal input to the switching unit.
There is also provided, in a second form, an interface method. The method includes receiving a first data signal operable for configuring a switching unit, and configuring the switching unit in a first configuration in response to a first predetermined value of the first data signal. A first plurality of data values is transferred from a first port to a buffer in response to the first configuration of the switching unit.
Additionally there is provided a test system. The system contains an automatic test equipment (ATE) and an interface apparatus. The interface apparatus includes a first port having a first maximum data rate and at least one second port having a second maximum data rate. The interface apparatus also includes a buffer; and a switching unit operable for transferring data between the first and at least one second ports and the buffer. The first port is operable for transferring a plurality of data values between the ATE and the interface apparatus. The transfer is in response to a first command signal input to the switching unit.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
REFERENCES:
patent: 6167492 (2000-12-01), Keller et al.
patent: 6286114 (2001-09-01), Veenstra et al.
patent: 6550033 (2003-04-01), Dwork
patent: 6584586 (2003-06-01), McCoy
patent: 6657966 (2003-12-01), Kramarczyk et al.
Brinkley Jeffrey
Rusk Leland Freddie
Advanced Micro Devices , Inc.
Britt Cynthia
De'cady Albert
Winstead Sechrest & Minick P.C.
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