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IEEE 1149.1 and P1500 test interfaces combined circuits and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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IEEE Std. 1149.4 compatible analog BIST methodology

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Image data test unit, image apparatus having the same, and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Immunity evaluation method and apparatus for electronic...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Implementation of an assertion check in ATPG models

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Implementation of boolean satisfiability with non-chronological

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Implementation of signature analysis for analog and mixed...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Implementation of test patterns in automated test equipment

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Implementing diagnosis of transitional scan chain defects...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Implementing enhanced array access time tracking with logic...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Implementing enhanced LBIST testing of paths including arrays

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Implementing isolation of VLSI scan chain using ABIST test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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In situ processor margin testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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In system diagnostics through scan matrix

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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In-chip monitoring system to monitor input/output of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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In-system programmable flash memory device with trigger...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Increasing the effectiveness of error correction codes and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Increasing the effectiveness of error correction codes and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Increasing the effectiveness of error correction codes and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Initial stage of a multi-stage algorithmic pattern generator...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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