Implementation of test patterns in automated test equipment

Details Implementation of test patterns in automated test equipment Implementation of test patterns in automated test equipment

2006-06-20

2006-06-20

Tu, Christine T. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S815000

Reexamination Certificate

active

07065693

ABSTRACT:
An improved automated testing system that decreases the number of test signals that must be stored in the tester pattern memory for a timed test pattern. In the present invention, a timed test pattern is controlled by a timing generator operable to change the timing interval of individual test cycles during the timed test pattern between first and second timing intervals, thereby decreasing the number of test signals stored in pattern memory for the timed test pattern. The method and apparatus of the present invention can be implemented to test integrated circuits comprising circuitry operating in first and second time domains wherein the first and second timing intervals of the timed test pattern correspond to the first and second time domains of the circuit, respectively.

REFERENCES:
patent: 6092225 (2000-07-01), Gruodis et al.
patent: 6138257 (2000-10-01), Wada et al.
patent: 6651205 (2003-11-01), Takahashi

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