Implementation of an assertion check in ATPG models

Details Implementation of an assertion check in ATPG models Implementation of an assertion check in ATPG models

2001-11-13

2004-08-31

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S744000

Reexamination Certificate

active

06785855

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to testing integrated circuit designs using automatic test pattern generation (ATPG). More particularly, the present invention relates to implementation of an assertion check in a scan cell used in ATPG to ensure that necessary conditions for performing an ATPG procedure are satisfied.
BACKGROUND OF THE INVENTION
An important step in the development and design of an integrated circuit is testing to detect faults in the circuit design. Testing of an integrated circuit generally involves adding partial or full scan to a circuit design using an ATPG program. The ATPG program generates a set of test patterns to identify faults in the integrated circuit design, which are applied to the input pins of the integrated circuit under test. The response of the integrated circuit to the test patterns is examined at the output pins of the integrated circuit to detect logic faults in the circuit design. A test pattern generally comprises a sequence of bits in the form of a vector, which is sequentially shifted through the storage elements of the integrated circuit.
FIG. 1
is a flow chart diagramming the steps involved in ATPG for testing an integrated circuit using an ATPG tool, such as FastScan or TetraMAX. A standard ATPG program generally initializes in step
10
by invoking a set of input information describing the integrated circuit under test. Typically, the input information comprises a netlist, such as a Verilog netlist, defining the circuit design and an ATPG library defining primitives and arrays for the circuit design. Verilog is a Hardware Description Language (HDL) for electronic design and gate level simulation and the netlist comprises a test file description of a physical connection of components in the circuit design. The ATPG program then switches to a setup mode and invokes a setup file containing list of commands in step
11
. Next, in step
12
, the ATPG program performs a scan extraction. Scan extraction involves reading the description of the circuit under test and calculating testability measurements for the circuit using design rules checking (DRC). The ATPG program identifies and debugs any design errors in the circuit in step
13
.
The ATPG program then proceeds to fault simulation and test pattern generation. Test pattern generation may be random, sequential, or fast sequence test pattern generation. Fault simulation is used to simulate the circuit design on a computer to facilitate the identification of defects in the actual circuit. During fault simulation, possible defects are inserted into the simulated circuit design to simulate and anticipate the response of the circuit to these defects. In step
14
, the ATPG program compiles a list of potential faults for the circuit and generates test patterns that simulate each fault in the list in step
15
. The test generation algorithm creates test patterns that simulate each of the potential fault types for the circuit under test. In step
16
, the test patterns are saved in various pattern formats. Generally, the test patterns are saved in Verilog, VHDL, EDIF or any suitable format. In step
17
, a fault coverage report is generated, which describes the percentage of potential faults from the fault list that are successfully simulated.
In step
18
, the test patterns are applied to a circuit under test and the output response is analyzed to identify faults in the circuit design. The circuit under test is switched to a test mode and the patterns generated by the ATPG tool are shifted through a scan portion of the circuit and output to an output pin. The scan portion comprises a set of storage elements, which form a shift register in test mode. During playback, the output test patterns shifted output the circuit and the vectors generated during fault simulation are compared by an output analyzer. The output analyzer compares the expected response of the circuit to the actual response of the circuit to diagnose and isolate faults that cause failures in the circuit. In step
19
, the results are printed to a file and a report identifying the faults detected in the circuit is generated.
“Scan design” refers to an electronic circuit design technique that facilitates testing of the circuit by making the storage elements of the circuit, which temporarily store logical states within the integrated circuit, scannable. Scan design involves incorporating scan registers into the circuit to form a scan path, thereby increasing the controllability and observability of the circuit. As discussed, the integrated circuit is tested by shifting a test vector generated by an ATPG program through the storage elements to ensure that the integrated circuit is functioning properly. Using scan design, the state of certain points in the circuit may be modified at any time by suspending normal operation and switching to a “test” mode. In standard operation, the shift registers perform normal operational tasks. The storage elements in the shift registers can be switched into a “test” mode and form a scan portion of the integrated circuit. During test mode, test pattern data can be clocked serially through all the scan registers and out of an output pin at the same time as new test pattern data is clocked in from an input pin.
Level Sensitive Scan Design (LSSD), developed by IBM, is a common type of scan design used with ATPG to test a circuit. LSSD uses separate system and scan clocks to distinguish between a standard operating mode and a test mode. In LSSD, level-sensitive latches used on-chip for state information are replaced by master-slave latch pairs, which are tied together into one long shift register. In standard operating mode, each storage-element is a level sensitive latch controlled by a system clock. For test operation, the latches form master/slave pairs, each pair having one scan input, one scan output and two non-overlapping scan clocks, which are held low during system operation but cause the scan data to be latched when pulsed high during scan. New state information is shifted in serially, allowing the core circuitry in the circuit to process this information, and shift out the modified state information to an output pin.
Current ATPG tools, such as those in the “FastScan” suite developed by Mentor Graphics and the “TetraMAX” suite developed by Synopsys, are used to analyze and classify probable defect sights using a simulation-based approach and a dynamic algorithm. However, many of the currently available ATPG tools used with LSSD cause significant fault coverage loss and test coverage loss and have a negative impact on the performance of the circuit. In other words, many potential design defects cannot be simulated and tested using these tools and of the design defects that can be simulated and tested for, many often go undetected.
In addition, prior scan cells used in ATPG lack a system for ensuring that necessary conditions are satisfied during testing. For example, in a circuit incorporating scan design, the scan cell can switch between a standard operating mode and a test mode, but cannot operate in both modes simultaneously. A system clock controls the input of data into the circuit during the standard operating mode and a scan clock controls the shifting of test pattern data through the scan portion of the circuit during test mode. The system clock and the scan clock must be independent and non-overlapping to differentiate between the standard operating mode and the test mode. Simultaneous activation of the system clock and the scan clock interferes with the shifting of test data through the circuit under test and results in significant inaccuracies and discrepancies Thus, it would be desirable to implement an assertion check to ensure that simultaneous activation of a system clock and a scan clock in a scan cell does not occur.
SUMMARY OF THE INVENTION
The illustrative embodiment of the present invention provides an assertion check in a design-for-test scan cell to ensure that necessary conditions for certain signals are satisfied. The assertion check includes an

Affiliated with

Also associated with

Rating

Implementation of an assertion check in ATPG models does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Implementation of an assertion check in ATPG models, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Implementation of an assertion check in ATPG models will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3283241