Implementing isolation of VLSI scan chain using ABIST test...

Details Implementing isolation of VLSI scan chain using ABIST test... Implementing isolation of VLSI scan chain using ABIST test...

2008-10-13

2011-11-22

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S736000

Reexamination Certificate

active

08065575

ABSTRACT:
A method, apparatus and computer program product are provided for implementing isolation of VLSI AC scan chain defects using structural Array Built In Self Test (ABIST) test patterns. An ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a passing operating region and each scan chain is unloaded. The ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a failing operating region for the device under test. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.

REFERENCES:
patent: 3761695 (1973-09-01), Eichelberger
patent: 5764655 (1998-06-01), Kirihata et al.
patent: 5983380 (1999-11-01), Motika et al.
patent: 6308290 (2001-10-01), Forlenza et al.
patent: 6996760 (2006-02-01), Dorsey
patent: 7020842 (2006-03-01), DeStefano et al.
patent: 7395469 (2008-07-01), Anderson et al.
patent: 7434130 (2008-10-01), Huisman et al.
patent: 2003/0036869 (2003-02-01), Huisman et al.
patent: 2004/0230882 (2004-11-01), Huott et al.
patent: 2005/0138514 (2005-06-01), Burdine et al.
patent: 2010/0095177 (2010-04-01), Forlenza et al.
patent: 2008082888 (2008-04-01), None
Makar, S.R.; McCluskey, E.J.; , “Functional tests for scan chain latches,” Test Conference, 1995. Proceedings., International , vol., No., pp. 606-615, Oct. 21-25, 1995 doi: 10.1109/TEST.1995.529889 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=529889&isnumber=11600.
Maka, S.R.; McCluskey, E.J.; , “ATPG for scan chain latches and flip-flops,” VLSI Test Symposium, 1997., 15th IEEE , vol., No., pp. 364-369, Apr. 27-May 1, 1997 doi: 10.1109/VTEST.1997.600306 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=600306&isnumber=13046.
Ruifeng Guo; Venkataraman, S.; , “A technique for fault diagnosis of defects in scan chains,” Test Conference, 2001. Proceedings. International , vol., No., pp. 268-277, 2001 doi: 10.1109/TEST.2001.966642 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=966642&isnumber=20866.
Yu Huang; Wu-Tung Cheng; Cheng-Ju Hsieh; Huan-Yung Tseng; Alou Huang; Yu-Ting Hung; , “Intermittent scan chain fault diagnosis based on signal probability analysis,” Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings , vol. 2, No., pp. 1072-1077 vol. 2, Feb. 16-20, 2004 doi: 10.1109/DATE.2004.1269035.
B. Konemann, J. Mucha, G. Zwiehoff, “Built-In Test for Complex Integrated Circuits”, IEEE Journal of Solid State Circuits vol. SC-15, pp. 315-318, Jun. 1980.
G. A. Sarrica, B. R. Kessler “Theory and Implementation of LSSD Scan Rind & STUMPS Channel Test and Diagnosis”, Sep. 28-3-, 1992, Electronics Manufacturing Technology Symposium, 1992I, Thirteenth IEEE/CHMT International, pp. 195-200.
R. Guo, S. Venkataraman, A Technique for Fault Diagnosis of Defects in Scan Chains, IEEE, paper 10.2, 2001 pp. 268-277, USA.
I. Bayraktaroglu et al., “Gate Level Fault Diagnosis in Scan-Based BIST,” Proceedings of the 2002 Design Automation and Test in Europe Conference, 1530-1591/02 IEEE.

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