Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-03-23
2002-04-02
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S742000, C714S736000
Reexamination Certificate
active
06367043
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention pertains to the field of very large scale integrated (VLSI) circuits employing both analog and mixed signal circuits and their testing using built-in self test (BIST) methods that employ signature analysis to determine whether a circuit/device is faulty or fault free.
At the present time there are no efficient methods to implement a BIST scheme that employs signature analysis to determine whether an analog or mixed signal circuit or device is faulty or fault free. Currently, signal processing systems, radar data analysis systems, cellular phone systems, etc., all use analog and mixed signal circuits which need to be tested during the production time in order to enhance production yield and after production to ensure the proper operation of the system. The present invention helps in testing these devices reliably and automatically at very high speeds thereby saving the industry millions of dollars. Current techniques are very slow and time consuming. For the most part, any company involved in the design of analog and mixed (analog & digital) signal circuits either in small or large scale, as application specific integrated circuits (ASIC) or as VLSI systems can use this invention in order to test their devices either at the production level or after production. The invention leads to rapid testing of analog and mixed signal systems.
Chin-Long Wey and S. Krishnan (I) have developed a BIST structure using “current copiers” as storage elements to monitor node currents at various nodes (test points) in an analog circuit. The current copiers are then concatenated to form a scan path (as shift registers in digital circuits) and the monitored currents are then scanned out to an output of the circuit/device where they will be compared with their expected values. If the difference between the scanned currents and their expected values lie within the specified tolerances, then the circuit/device is judged to be fault free else it is Judged to be faulty. This scheme based on current copiers is difficult to implement and occupies excessively large silicon area in a very large scale integrated (VLSI) circuit as the current copiers employ large capacitors for storing the currents that are monitored. Moreover, the scheme requires a large storage (memory) in a computer to store the expected values of the monitored currents at various nodes in a circuit. The present invention overcomes both of the drawbacks of the BIST scheme proposed by Chin-Long Wey and S. Krishnan (I). Moreover, the BIST scheme in this invention is based on signature analysis while the BIST scheme proposed by Chin-Long, Wey and S. Krishnan (1) is not. The present invention uses sample and hold (SH) circuits for storing monitored currents at various nodes and shifting them by forming scan paths. Instead of comparing the monitored currents with their stored expected values, the monitored currents will be used to generate a signature consisting of only few digits using a linear feedback shift register (LFSR) or multiple input shift register (MISR). The signature for the circuit is then compared with a reference signature. Thousands of monitored currents are compressed into a signature of 20 or fewer digits. Hence, instead of storing thousands of values, one needs to store a signature of, at most, 20 digits. This invention presents the practical implementation of such a BIST scheme and the design of its building blocks.
The present invention responds to the shortcomings, drawbacks and limitations of prior art BIST schemes, and the need for simple and elegant BIST schemes based on signature analysis to test VLSI devices ever increasing in size and complexity. This invention makes testing of VLSI devices consisting of analog and mixed signal circuits easy and automatic. Prior art approaches, methods and techniques are described in the following publications:
(1). Chin-Long Wey and S. Krishnan, “Built-In Self Test (BIST) Structures for Analog Circuit Fault Diagnosis with Current Test Data,” IEEE Trans. on Instrumentation and Measurement, Vol, 41, No. 4, August 1992, pp. 535-539.
(2) Mani Soma, “Structure and Concepts for Current-Based Analog Scan,” Proc. of 1995 Custom Integrated Circuits Conference. Santa Clara, Calif., pp. 517-520.
(3) S. J. Daubert, D. Vallancourt, and Y P. Tsivids, “Current copier cells,” Electronics Letters, Vol. 24, December 1988, pp. 1560-1562.
(4) D. L. Rhodes, G. Tempel and M. Cummings, “Application of Fault Modeling to Continuous Built-In Test (c-BIT) for Microwave and MMIC Circuits,” Intl. Jour. of Microwave and Millimeterwave CAD (vol. date, pp.).
SUMMARY OF THE INVENTION
In this application several publications are referenced by Arabic numerals in brackets. Full citations for these publications may be found at the end of the written description immediately preceding the claims. The disclosures of all such publications, in their entireties, are hereby expressly incorporated by reference in this application as if fully set forth, for purposes of indicating the background of the invention and illustrating the state of the art.
Traditionally, signature analysis has been used very successfully for detecting faults in digital systems. In fact, it has become the de-facto standard for detecting faults in digital systems. One of the things that contributes to signature analysis in digital systems is the use of scan path designs (1, 2), which allow the operation of digital systems in two distinct modes, namely, system mode operation and test mode operation. In system mode operation, the system operates normally. In test mode operation, test patterns are applied to the circuit under test (CUT) one at a time and its outputs are applied to a signature generator. At the end of application of all test vectors, what remains in the signature generator is referred to as the “signature.” For any fault-free circuit, this signature should be the same as the reference signature, and for faulty circuits, to a high degree of probability, it is different. So one is able to compare the signature generated by a CUT with the reference signature (signature for a fault-free circuit) and determine whether the CUT is faulty or fault free. Due to its simplicity and ease of implementation, signature analysis has become a very useful tool. However, in analog circuits, implementation of signature analysis is difficult for several reasons. While in digital systems the data is always well defined in terms of a “0” state and a “1” state, corresponding to logical zero and logical one output voltages of a digital circuit, in analog systems the output voltage or current of a circuit or a node has no well-defined state. Moreover, the node voltage/current can vary within the specified tolerances as a result of variations in discrete components such as resistors, capacitors, inductors, transistors, etc. Unlike in digital circuits, analog shift registers are difficult to construct, and signature analyzers are essentially discrete in nature.
Prior art techniques utilize current copiers (8, 15) for scan designs. Sample and hold circuits employing “current mode” operation are used to store and shift data, similar to master-slave flip-flops (3,9) in digital systems, which led to scan path designs. Whether current copiers or current-mode sample and hold circuits are used in scan path designs, testing basically consists of monitoring currents at various test points (nodes) in a CUT and shifting these currents to an output port using scan paths. The node currents shifted to an output are then compared with their stored expected values to verify whether the circuit is functioning within the specified tolerances. If any of the node currents is found to be beyond the specified tolerance limits, the CUT is declared faulty. Since no data compression is used or signature generated, the amount of reference data that must be stored is very large. In order to avoid large storage, more often than not, one resorts to limiting the number of test points and number of test vectors used for testi
Clohan, Jr. Paul S.
Stolarun Edward L.
The United States of America as represented by the Secretary of
Tu Christine T.
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