Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-06-22
2003-11-18
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S731000, C365S185330
Reexamination Certificate
active
06651199
ABSTRACT:
FIELD OF INVENTION
The present invention relates to In-System Programmable (ISP) Flash memory devices. In particular, it relates to ISP Flash memory devices that incorporate JTAG test circuitry.
BACKGROUND OF THE INVENTION
In-System Programmable (ISP) Flash memory devices are programmable logic devices (PLDs) that make use of electrically erasable and programmable Flash memory cells and are capable of being programmed or re-programmed while mounted on a system board. ISP refers to the entire process of programming a device in-system, and, therefore, encompasses the actions of erasing and verifying the design in the device in addition to the specific action of memory cell programming. ISP allows for speedier product development and facilitates the process of improving a PLD in a system.
Some ISP Flash devices contain a so-called JTAG interface through which a user can program the device. This interface is a standard specified in “IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE Std 1149.1-1990 (includes IEEE Std 1149.1a-1993), published by the Institute of Electrical and Electronics Engineers, Inc. on Oct. 21, 1993. The JTAG standard creates a means of verifying the integrity of traces between components on an assembled printed circuit board by providing a standard architecture and a set of mandatory public instructions that all vendors claiming conformance to IEEE standard 1149.1 must support.
When programming Flash memory using a JTAG interface, a JTAG instruction register circuit (i.e., an instruction register and instruction decoder) shifts instruction data and an internal statemachine (TAP controller) is required to control the programming states and time. Generally, JTAG-based operating systems issue a general program instruction (INSTN), which then initiates a JTAG RUN-TEST signal. When both INSTN and RUN-TEST signals are asserted, the TAP controller begins a program state (or similarly the erase, blank check or program verify states), and programming of the ISP Flash device is ultimately initiated. When programming is finished, the TAP controller goes into a discharge state where the logic high voltage signals INSTN and RUN-TEST are discharged, followed by returning to an idle state. Typically, the programming state lasts approximately 5 msec, and the discharge state lasts approximately 18 &mgr; sec.
A problem is associated with JTAG-based operating systems, however. Shifting program instruction data with the JTAG instruction register circuit and changing the state of the TAP controller requires several clock cycles for completion. Accordingly, a particular set of instruction signals (e.g., RUN-TEST and INSTN) may be maintained for a longer period of time than is necessary to perform a desired operation. As a result, the programming operation for a row of memory cells may be completed, and the TAP controller may return to an idle state before the RUN-TEST and INSTN signal are changed. When this occurs, conditions hold for a second programming operation for the already-programmed row of memory cells, which can produce undesirable programming states in the Flash memory cells.
It is therefore desirable to have a circuit that changes the JTAG instruction signals into limited duration instructions signals that toggle high long enough to initiate the program, erase, blank check or program verify functions and then toggle low to prevent repeating the operation before the JTAG RUN-TEST and INSTN signals can be changed.
SUMMARY OF THE INVENTION
The present invention provides an ISP Flash memory device that addresses the problem discussed above.
In accordance with the present invention, an ISP Flash memory device includes a trigger circuit for generating instruction signals that control the operating state of a control state machine so that it transmits appropriate control signals to a memory circuit during the various operations performed by the ISP Flash memory device. The trigger circuit prevents a second programming operation once the row of memory cells has already been programmed by changing the instruction signal received from a JTAG instruction decoder into a limited duration instruction signal that toggles high only long enough to effect the desired state change in the control state machine.
The trigger circuit includes a first AND gate, a delay circuit, an inverter and a second AND gate. The first AND gate has input terminals connected to receive a RUN-TEST signal from a JTAG TAP controller and an instruction signal. It generates a logic high output signal when both the RUN-TEST and instruction signals are asserted. The delay circuit also has an input terminal connected to receive the RUN-TEST signal. It generates a logic high output a predetermined number of clock cycles after the RUN-TEST signal is asserted. The inverter is connected to the output terminal of the delay circuit. Finally, the second AND gate has a first input terminal connected to an output terminal of the first AND gate, a second input terminal connected to an output terminal of the inverter, and an output terminal for transmitting a pulse instruction signal to a control state machine. The control state machine includes a logic AND gate that generates a high control signal when both the pulse instruction signal received from the trigger circuit and the RUNT-TEST signal received from the JTAG TAP controller are asserted.
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Bever Patrick T.
Cartier Lois D.
De'cady Albert
Moore William
Xilinx , Inc.
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