In situ processor margin testing

Details In situ processor margin testing In situ processor margin testing

2006-08-25

2010-02-16

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C718S001000

Reexamination Certificate

active

07665005

ABSTRACT:
Embodiments of apparatuses, methods, and systems for in situ processor margin testing are disclosed. In one embodiment, an apparatus includes virtual machine control logic and operating point control logic. The virtual machine control logic is to transfer control of the apparatus between a virtual machine monitor and a guest. The operating point control logic is to set the operating point of the apparatus in connection with a transfer of control of the apparatus to the virtual machine monitor.

REFERENCES:
patent: 7124327 (2006-10-01), Bennett et al.
patent: 7191440 (2007-03-01), Cota-Robles et al.
patent: 2008/0282241 (2008-11-01), Dong

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