Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-06-05
2007-06-05
Britt, Cynthia (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
11211092
ABSTRACT:
An analog built-in self-test (BIST) methodology based on the IEEE 1149.4 mixed signal test bus standard. The on-chip generated triangular stimuli are transmitted to the analog circuit under test (CUT) through the analog test buses, and their test responses are quantized by the dual comparators. The quantized results are then fed into a pair of counters to record the sampled counts for comparison in the decision circuit. A pass/fail indication is then generated in the decision circuit to indicate success or failure of the CUT after the BIST operation is complete.
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patent: 2002/0099990 (2002-07-01), Sunter
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Lin Shyh-Horng
Su Chau-chin
Wang Laung-Terng (L.-T.)
Britt Cynthia
Syntest Technologies, Inc.
Zegeer Jim
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