IEEE Std. 1149.4 compatible analog BIST methodology

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Reexamination Certificate

active

11211092

ABSTRACT:
An analog built-in self-test (BIST) methodology based on the IEEE 1149.4 mixed signal test bus standard. The on-chip generated triangular stimuli are transmitted to the analog circuit under test (CUT) through the analog test buses, and their test responses are quantized by the dual comparators. The quantized results are then fed into a pair of counters to record the sampled counts for comparison in the decision circuit. A pass/fail indication is then generated in the decision circuit to indicate success or failure of the CUT after the BIST operation is complete.

REFERENCES:
patent: 6492798 (2002-12-01), Sunter
patent: 7032151 (2006-04-01), Halder et al.
patent: 7102555 (2006-09-01), Collins et al.
patent: 2002/0099990 (2002-07-01), Sunter
IEEE Standard for a Mixed Signal Test Bus, IEEE Std. 1149.4, IEEE, 1999.
C. Su and Y.T. Chen, “Intrinsic Response Extraction for the Analog Test Bus Parasitic Effect Removal,”IEEE Trans. on Computer-Aided Design, vol. 19, No. 4, pp. 437-445, Apr. 2000.
S. Sunter, K. Filliter, W. Joe, and P. McHugh, “A General Purpose 1149.4 IC with HF Analog Test Capabilities,”Prof. Int'l Test Conf., pp. 38-45, 2001.
G.O.G. Acevedo and J. Ramirez-Angulo, “Built-in Self-Test Scheme for On-chip diagnosis, Compliant with the IEEE 1149.4 Mixed Signal Test Bus Standard,”Proc. IEEE Int'l Symp. on Circuits and Systems, pp. 26-29, 2002.
C. Su, C.-H. Wang; W.-J. Wang; and I.S. Tseng, “1149.4 Based On-Line Quiescent State Monitoring Technique,”Proc. IEEE VLSI Test Symp., pp. 197-202, 2003.

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