In-chip monitoring system to monitor input/output of...

Details In-chip monitoring system to monitor input/output of... In-chip monitoring system to monitor input/output of...

2005-05-24

2005-05-24

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06898750

ABSTRACT:
An in-chip monitoring method and apparatus are disclosed. In one embodiment the apparatus includes a test pad, a transmission gate and a plurality of test components coupled to the transmission gate. The transmission gate is attached to a substrate and adapted to receive a code word uniquely addressed to one of the plurality of test components. In a further embodiment, the transmission gate is further adapted to relay an output of the one of the plurality of test components to the test pad, in response to receipt of the code word.

REFERENCES:
patent: 4947357 (1990-08-01), Stewart et al.
patent: 5115437 (1992-05-01), Welles, II et al.
patent: 5734661 (1998-03-01), Roberts et al.
patent: 5774475 (1998-06-01), Qureshi
patent: 0 639 006 (1995-02-01), None
patent: WO 0133238 (2001-05-01), None

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