Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-07-26
2010-10-26
Ellis, Kevin L (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S732000, C365S201000, C324S765010
Reexamination Certificate
active
07823033
ABSTRACT:
A data processing system includes functional circuitry which performs at least one data processing function, a register file coupled to the functional circuitry and having a plurality of general purpose registers (GPRs) which are included as part of a user's programming model for the data processing system, where a portion of the plurality of GPRs are reconfigurable as test registers during a test mode, and control circuitry which provides a test enable indicator to the register file. The portion of the plurality of GPRs, in response to the test enable indicator indicating the test mode is enabled, operates to accumulate test data from predetermined circuit nodes within the functional circuitry. In one aspect, the portion of the plurality of GPRs are reconfigured as multiple input shift registers (MISRs) during the test mode and generate signatures based on the test data.
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Gumulja Jimmy
Moyer William C.
Chiu Joanna G.
Ellis Kevin L
Freescale Semiconductor Inc.
King Robert L.
Merant Guerrier
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