Data retaining boundary scan cell

Details Data retaining boundary scan cell Data retaining boundary scan cell

2007-10-09

2007-10-09

Chase, Shelly (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

10609757

ABSTRACT:
Scan testing of plural target electrical circuits, such as circuits1through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit1, as the scan test stimulus data for another circuit, such as circuit2. After reset, a scan path captures the output response data from the reset stimulus from all circuits. A tester then shifts the captured data only the length of the first circuit's scan path while loading the first circuit's scan path with new test stimulus data. The new response data from all the circuits then is captured in the scan path. This shift and capture cycle is repeated until the first circuit is tested. The first circuit is then disabled and any remaining stimulus data is applied to the second circuit. This process is repeated until all the circuits are tested. A data retaining boundary scan cell used in the scan testing connects the output of an additional multiplexer as the input to a boundary cell. The inputs of the additional multiplexer connect to the data input and data output of the boundary cell.

REFERENCES:
patent: 5568492 (1996-10-01), Flint et al.
patent: 5596584 (1997-01-01), Warren
patent: EP 0514700 (1992-11-01), None

Affiliated with

Also associated with

Rating

Data retaining boundary scan cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data retaining boundary scan cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data retaining boundary scan cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3897837