Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-02-12
2000-11-07
DeCady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714 30, 714733, 714734, G01R 3128
Patent
active
061451045
ABSTRACT:
An integrated circuit containing a data processing system with a number of external peripheral pins utilizes the peripheral pins for both testing the corresponding peripherals and for parallel testing of other complex functions in a MCU. The MCU has a plurality of test modes that can be selected, with different peripheral pins being connected to a test circuit depending on which test mode is selected. This allows testing of peripherals via their corresponding pins, as well as other complex functions without the necessity of having dedicated test pins.
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Feddeler James R.
Getka William Edward
Thompson Daniel Mark
Wood Michael Charles
De'cady Albert
Lin Samuel
Motorola Inc.
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