Data communication interface with memory access controller

Details Data communication interface with memory access controller Data communication interface with memory access controller

1997-09-23

2000-07-04

Baker, Stephen M.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714718, G01R 313185

Patent

active

060853441

ABSTRACT:
A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included on circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple shift operations.

REFERENCES:
"Test Bus Architecture", IBM Technical Disclosure Bulletin, vol. 32, No. 3A, Aug. 1989, pp. 21-27, Aug. 1989.

Affiliated with

Also associated with

Rating

Data communication interface with memory access controller does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data communication interface with memory access controller, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data communication interface with memory access controller will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1496626