Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-04-07
2003-05-20
Decady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06567943
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to integrated circuitry and, in particular, to a boundary scan cell of an integrated circuit. Still more particularly, the present invention relates to a high-performance IEEE1149.1-compliant boundary scan cell of an integrated circuit.
2. Description of the Related Art
A significant expense incurred during the manufacture of circuit cards carrying one or more integrated circuit components is testing. Such testing generally entails stimulating the input/output (I/O) pins of a circuit card with a predetermined pattern of inputs and then observing the outputs generated by the components residing on the circuit card. Several factors contribute to the expense of circuit card testing. First, because many circuit card components do not employ a standard I/O interface, circuit card testing fixtures tend to be complex and must often be custom-designed to test particular circuit cards. Second, the input pattern utilized to stimulate a circuit card must often be generated manually in order to ensure that circuit card components are exercised over a sufficient range of functionality to ensure high quality. Third, while it may be less expensive for a circuit card or component manufacturer to out-source testing to an outside contractor, the use of non-standard component interfaces can require the component manufacturer to reveal proprietary information concerning the internal design of a component to the component tester, making many manufacturers reluctant to engage an outside contractor to perform testing.
In order to decrease the cost and increase the quality of component testing, the IEEE (Institute of Electrical and Electronic Engineers) adopted IEEE Std 1149.1, which is defined by the Standard Test Access Port and Boundary-Scan Architecture,
Institute of Electrical and Electronics Engineers
(May 21, 1990) and the 1149.1b-1994 Supplement, which are incorporated herein by reference. The IEEE1149.1 standard specifies that a boundary scan cell be inserted between the functional logic of a component and each of its input receiver and output driver circuits. These boundary scan cells, whose behavior is prescribed in detail by the IEEE1149.1 standard, are typically implemented with one or more 2-to-1 multiplexers in the direct path between the component's output flip-flop and driver or between the component's receiver and input flip-flop.
For example, referring now to
FIG. 1
, there is depicted a high level block diagram of a conventional high performance boundary scan cell
10
coupled to an edge-sensitive D flip-flop
14
for storing and launching data from system logic and a scan-path multiplexer
12
. As shown, boundary scan cell
10
includes a mode multiplexer
16
in the path between D flip-flop
14
and the output buffer. Boundary scan cell
10
further includes a shift multiplexer
18
, a shift latch
20
and an update latch
22
. In operation, scan-path multiplexer
12
selects between the functional logic signal and scan path data in response to a scan enable (SE) signal. The output signal of scan-path multiplexer
12
is propagated through D flip-flop
14
to mode multiplexer
16
, which selects either the output signal of D flip-flop
14
or the output signal of update latch
22
in response to the state of a MODE signal indicating whether the circuit is operating in test mode. As can be seen in
FIG. 1
, a conventional boundary scan cell subjects the functional logic signal to the delay of at least one 2-to-1 multiplexer between the system output flip-flop and the output buffer.
Thus, while the implementation of conventional IEEE1149.1-compliant interfaces within components facilitates higher quality, low cost testing without the need for disclosure of the internal circuitry of the components under test, these benefits come at the expense of performance due to the signal path delay associated with a multiplexer in the functional signal path and the loading associated with conventional boundary scan cells. Because of the performance penalty associated with conventional IEEE1149.1-compliant boundary scan cells, manufacturers have resisted compliance with the IEEE1149.1 standard.
To avoid the performance penalty associated with conventional boundary-scan cell implementations while still retaining compliance with the IEEE 1149.1 standard, efforts have recently been directed to reducing or eliminating the multiplexer delay described above. For example, U.S. Pat. No. 5,615,217 to Horne et al. discloses a method and apparatus for bypassing a boundary-scan cell during functional operation of an associated electronic component in order to avoid the component output signal traversing a multiplexer after a transition in the clock signal of the component. However, the solution proposed by Horne et al. still requires a multiplexer in the functional data path, which entails a concomitant delay that must be accounted for in meeting signal timing constraints. In addition, the scan path includes two multiplexers and two data latches, which adversely impacts testing performance. Another approach, which is disclosed in the application cross-referenced above, improves upon the conventional approach by implementing the output latch of the boundary-scan cell circuitry as an enhanced shift register latch (SRL) into which the function of the output multiplexer is merged. Although this approach improves upon the prior art by eliminating the output multiplexer, the resulting SRL does not provide as good of performance as other SRL configurations.
SUMMARY OF THE INVENTION
The present invention improves upon the prior art and overcomes the above-noted shortcomings in the art by providing an improved IEEE1149.1-compliant boundary scan cell that reduces the number of multiplexer delays in the functional signal path and supports high-performance testing.
In accordance with the present invention, a boundary scan cell includes a shift latch, an update latch and a flushable latch that each have at least a respective data input and at least a respective data output. The data output of the shift latch is coupled to the data input of the update latch. The boundary scan cell further includes control circuitry that controls operation of the flushable latch circuit. The control circuitry selects, as input data for the flushable latch, one of a functional logic signal and a boundary scan signal in response to a mode signal. If the mode signal indicates a test mode, the control circuitry selects the boundary scan signal as the input data and causes the flushable latch to flush through the input data to the data output of the flushable latch independent of a system clock signal. The boundary scan cell can be implemented as either an input or output cell and preferably is compliant with IEEE Std 1149.1.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
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patent: 5615217 (1997-03-01), Horne et al.
patent: 5631911 (1997-05-01), Whetsel, Jr.
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Groves et al., “High-Performance CMOS Register”, vol. 33, No. 3B, Aug. 1990, pp. 363-366.
Barnhart Carl Frederick
Lackey David
Oakland Steven Frederick
Bracewell & Patterson L.L.P.
Britt Cynthia
De'cady Albert
Henkler Richard A.
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