Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-07-05
2005-07-05
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S025000, C714S724000
Reexamination Certificate
active
06915470
ABSTRACT:
In a data log acquisition circuit100, the number of executed test patterns counted by a number-of-patterns counter1, or the address of the test pattern is compared with a predetermined reference value by an identity detection circuit2. If the number of executed test patterns or the address of the test pattern and the predetermined reference value are data for the same test pattern, an identity signal is supplied to a log mode control circuit3. The address of the test pattern is written into a log memory6at timing adjusted by a timing adjustment circuit4correspondingly to a write address of a data log generated by a counter5in accordance with an established operation mode. The write address and the address of the test pattern are held temporarily by a flip-flop9. The number of generated FAIL signals is counted and outputted by a counter10.
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patent: 6587983 (2003-07-01), Nakayama
Ando Electric Co. Ltd.
Fish & Richardson P.C.
Lamarre Guy J.
Trimmings John P.
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