Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-03-27
2000-12-05
Moise, Emmanuel L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714729, 324 731, 324763, G01R 3128
Patent
active
061580325
ABSTRACT:
A data processing system, circuit arrangement, program product, and method thereof utilize a multi-path scan interface that is capable of providing multiple scan paths into a plurality of scan ring segments in an integrated circuit device. The multi-path scan interface utilizes one or more multiplexers coupled between scan in and scan out ports and at least one scan ring segment to provide alternate scan paths depending upon select signals supplied to each multiplexer. With such a configuration, a standardized scan interface may developed for interfacing with a wide variety of scan ring segments, and optionally, for multiple purposes. As a result, the amount of custom circuitry necessary to provide access to scan ring segments is significantly reduced.
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Currier Guy Richard
Day Leland Leslie
Douskey Steven Michael
Ganfield Paul Allen
Wallin James Maurice
International Business Machines - Corporation
Moise Emmanuel L.
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