Circuit to prevent inadvertent test mode entry
Circuit with expected data memory coupled to serial input lead
Circuitry for and system and substrate with circuitry for...
Circuitry for handling high impedance busses in a scan...
Circuitry to prevent peak power problems during scan shift
Circuitry with multiplexed dedicated and shared scan path cells
Circuits and associated methods for improved debug and test...
Circuits and methods for testing logic devices by modulating...
Circuits and methods for testing programmable logic devices...
Clock adjusting method and circuit device
Clock adjusting method and circuit device
Clock control circuit for test that facilitates an at speed...
Clock controller for at-speed testing of scan circuits
Clock delay circuits and multiplexer connected to boundary...
Clock domain test isolation
Clock duty cycle based access timer combined with standard...
Clock generator and method for providing reliable clock...
Clock skew insensitive scan chain reordering
Clock transferring apparatus, and testing apparatus
Clocking methodology for at-speed testing of scan circuits...