Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2003-06-13
2004-05-11
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C713S401000, C326S093000
Reexamination Certificate
active
06735732
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to clock adjusting methods and circuit devices, and more particularly to a clock adjusting method for a device which uses a flip-flop for input and output, and to a circuit device which employs such a clock adjusting method.
Recently, in electronic computers and the like, delay type (D-type) flip-flops are arranged between the input and output of circuits, and signals are transmitted by synchronizing the D-type flip-flops by a clock. If there exists a path having a slow signal transmission between the D-type flip-flops, it may not be possible to transmit and receive the signals. For this reason, the clock phase of the D-type flip-flop on the transmitting side and the clock phase of the D-type flip-flop on the receiving side are adjusted to optimum values.
On the other hand, due to increasing operating speeds of electronic computers, the frequency of the clock is also increasing. Consequently, there are demands to increase the adjusting accuracy with which the phase error between the clock of the transmitting side D-type flip-flop and the receiving side D-type flip-flop is adjusted.
2. Description of the Related Art
FIG. 1
is a system block diagram showing an example of a conventional circuit device. In
FIG. 1
, a signal processing circuit
1
and a signal processing circuit
2
are coupled via a transmission path
3
. A D-type flip-flop
4
is provided at a signal output part of the signal processing circuit
1
. On the other hand, a D-type flip-flop
5
is provided at a signal input part of the signal processing circuit
2
.
External clocks CLKA and CLKB are respectively supplied to the D-type flip-flops
4
and
5
. The clocks CLKA and CLKB which are supplied to the D-type flip-flops
4
and
5
are originated from a clock oscillator
6
. A clock generated from the clock oscillator
6
is supplied to the D-type flip-flop
4
via a delay adjusting circuit
7
as the clock CLKA on one hand, and is supplied to the D-type flip-flop
5
via a delay adjusting circuit
8
as the clock CLKB on the other.
Delay quantities (or delay times) of the delay adjusting circuits
7
and
8
are set by taking into consideration the delay of the transmission path
3
and the delays of the clocks CLKA and CLKB supplied to the D-type flip-flops
4
and
5
. In other words, optimum values of the delay quantities of the delay adjusting circuits
7
and
8
are calculated so as to supply the clocks CLKA and CLKB to the respective D-type flip-flops
4
and
5
so that the signal transmitted from the D-type flip-flop
4
can be accurately received by the D-type flip-flop
5
. The calculated optimum values are set to the delay adjusting circuits
7
and
8
as they are, as the delay quantities.
FIG. 2
is a system block diagram showing another example of the conventional circuit device. In
FIG. 2
, those parts which are the same as those corresponding parts in
FIG. 1
are designated by the same reference numerals, and a description thereof will be omitted.
In
FIG. 2
, a test pattern generating circuit
10
and a selector
9
are provided on the transmitting side, and a test pattern generating circuit
11
and a comparator circuit
12
are provided in the receiving side.
When making the adjustment, the selector
9
on the transmitting side selects an output test pattern of the test pattern generating circuit
10
. The selected output test pattern is held by the D-type flip-flop
4
, and is transmitted to the D-type flip-flop
5
via the transmission path
3
. On the other hand, at the receiving side, the comparator circuit
12
compares the test pattern received by the D-type flip-flop
5
and a test pattern which is generated from the test pattern generating circuit
11
, so as to judge whether or not the signals are correctly transmitted. The above described operation is carried out while varying the delay quantities of the delay adjusting circuits
7
and
8
, so as to determine the delay quantities with which a correct comparison result is obtained at the comparator circuit
12
.
However, according to the clock adjusting method described with reference to
FIG. 1
, the delay quantities of the delay adjusting circuits are calculated from the delay of the transmission path and the like, and the calculated delay quantities are set in the delay adjusting circuits. For this reason, there is a problem in that it is impossible to adjust inconsistencies which are inevitably introduced among the individual circuit devices due to production inconsistencies.
In addition, in a case where the test pattern generating circuits are provided in the circuit device in order to measure the delay quantities for each individual circuit device, as described with reference to FIG.
2
. there is a problem in that the circuit construction of the circuit device becomes complex due to the provision of the test pattern generating circuits.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful clock adjusting method and circuit device, in which the problems described above are eliminated.
Another and more specific object of the present invention is to provide a clock adjusting method and circuit device, which can adjust clocks of individual circuit devices using a relatively simple circuit construction.
Still another object of the present invention is to provide a clock adjusting method for adjusting a first clock supplied to a first flip-flop which is coupled to an output of a first circuit and a second clock supplied to a second flip-flop which is coupled to an input of a second circuit, the first and second flip-flops being coupled via a transmission path, where the clock adjusting method comprises the steps of (a) transmitting data from the first flip-flop to the second flip-flop via the transmission path while varying delay quantities of the first and second clocks, (b) obtaining a combination of the delay quantities of the first and second clocks with which the data is correctly transmitted from the first flip-flop to the second flip-flop, and (c) adjusting the delay quantity of at least one of the first and second clocks based on the combination so as to synchronize operations of the first and second flip-flops. According to the clock adjusting method of the present invention, it is possible to easily adjust the clock without the need to set test patterns.
A further object of the present invention is to provide a clock adjusting method for adjusting a first clock supplied to an output flip-flop and a second clock supplied to an input flip-flop in a circuit device so as to synchronize operations of the output flip-flop and the input flip-flop, the output flip-flop holding a state of an output signal of a signal processing circuit, the input flip-flop holding a state of a signal output from the output flip-flop, the first clock being output from a first adjusting circuit which delays a clock from a clock oscillator, the second clock being output from a second adjusting circuit which delays the clock from the clock oscillator, where the clock adjusting method comprises an output state detecting procedure, detecting output signal states of the output flip-flop and the input flip-flop by repeating an operation of controlling the clock oscillator to supply the first clock to the output flip-flop and the second clock to the input flip-flop while varying delay quantities of the first and second adjusting circuits, and a delay quantity setting procedure, detecting a combination of delay quantities of the first and second adjusting circuits with which the output signal state of the output flip-flop is correctly transmitted to the input flip-flop, based on the output signal states of the output flip-flop and the input flip-flop detected by the output state detecting procedure, and setting the delay quantities of the first and second adjusting circuits depending on the detected combination. According to the clock adjusting method of the present invention, it is possible to e
De'cady Albert
Dooley Matthew C.
Fujitsu Limited
Westerman Hattori Daniels & Adrian LLP
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