Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-09-19
2006-09-19
DeCady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000, C714S736000, C326S039000, C326S041000
Reexamination Certificate
active
07111214
ABSTRACT:
Circuit implementations and test methods enable the testing of lookup table (LUT) input paths, “stuck at” memory cell values, and carry chains. One method includes storing a first bit pattern in each LUT, configuring the carry chain to perform a wide AND function of the LUT outputs, and cycling the inputs of each LUT while comparing the carry chain output to an expected value and reporting the PLD faulty if a difference is detected. The carry chain is configured to perform a wide OR function, and the cycling step is repeated. The bit pattern within each LUT is changed to the complement of the first bit pattern by providing a series of shift commands or by otherwise storing new values in the LUT, and the configuring and cycling steps are repeated. The invention also provides PLD circuit implementations that can be used to perform the described methods.
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Chaudhary Kamal
Krishnamurthy Sridhar
Cartier Lois D.
DeCady Albert
Maunu LeRoy D.
Tabone, Jr. John J.
Xilinx , Inc.
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