Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-06-22
2001-09-04
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S734000, C714S736000, C324S073100
Reexamination Certificate
active
06286117
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of electronics in general and to electronics testing in particular.
BACKGROUND OF THE INVENTION
Logic devices may operate according to logical inputs and voltage supplies provided to the logic devices. The logic devices may be subjected to noise and variations in power levels as a result of the electrical characteristics of the system in which the logic devices operate.
Logic devices may be tested as stand-alone devices or in groups that estimate the electrical characteristics of the system in which the logic devices operate. In general, conventional testing systems may provide test inputs and a voltage supply to the logic devices and examine the resulting outputs generated by the logic devices in response to the test inputs. For example, test inputs may include patterns of signal levels that generate a corresponding response from the logic devices. If the logic devices are functioning properly, the response corresponds to the test inputs. The logic devices may, thereby, be accepted or rejected based on the response of the logic devices when subjected to the test inputs and voltage supply.
Conventional testing systems may provide the test inputs and voltage supply described above during a particular phase of the test procedure. For example, the testing system may provide the test inputs and voltage supply during a first testing phase. When the first testing phase ends, the system may provide new test inputs and voltage supply corresponding to a second phase of testing. As the performance and complexity of logic devices increase, there is an increasing need for improved testing of logic devices.
SUMMARY OF THE INVENTION
In view of the above discussion, it is an object of the present invention to provide improved testing of logic devices.
It is another object of the present invention to provide improved noise testing of logic devices.
These and other objects of the present invention are provided by circuits, methods, and systems that introduce noise into test inputs and voltage supplies provided to the logic devices while under going testing by modulating a test voltage output with a noise signal to produce the test input. In particular, a noise signal and a test voltage output are generated. The test voltage output is modulated with the noise signal to provide a test input to the logic device. The present invention may thereby provide a test input that may allow a more accurate representation of a system having noise, by approximating an actual operating environment for the logic device under going testing.
The noise generator can produce an analog signal or a clock signal to be used as the noise component of the test input. For example, the noise generator can provide a clock signal that is combined, via the modulator, with the test voltage output to produce an approximation of switching noise in the test input to the logic device. The noise signal can include a pseudo-random noise signal or a periodic signal.
In one aspect, the noise generator is a clock signal generator that produces a clock signal having a clock signal amplitude and a clock signal frequency. The present invention may thereby provide a noise component of the test input having an amplitude and a frequency that can be controlled. The noise generator can also produce a noise signal having a variable frequency and amplitude. The present invention may thereby allow a more accurate representation of the noise found in actual systems using the logic devices under going testing.
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Jung Ki-hun
Kim Yun-ki
Park Hyun-deok
Yun Sung-jun
Moise Emmanuel L.
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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