Clock skew insensitive scan chain reordering

Details Clock skew insensitive scan chain reordering Clock skew insensitive scan chain reordering

1996-05-22

2003-03-25

Iqbal, Nadeem (Department: 2184)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000

Reexamination Certificate

active

06539509

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of laying out complex circuit designs and more particularly to a method of reordering a scan chain based on the results of distributing a clock signal to eliminate any scan chain hold time failures and minimize chip area overhead required for the scan chain.
BACKGROUND OF THE INVENTION
Integrated circuits utilize a clock signal to control the timing of combinatorial (gates) and sequential (latches, flip-flops) circuit elements contained therein. Ideally, this clock signal must reach the various elements that are physically distributed throughout the integrated circuit at the same time. If the elements are located at varying distances from the source of the clock signal, the clock signal will arrive at different times to the elements over the interconnecting metal leads. This is one cause of a phenomenon known as clock skew. Clock skew can also be caused by the resistance and the capacitance encountered by the clock signal to the various elements. Techniques to compensate for this cause of clock skew include designing the metal leads to have equivalent length and capacitively loading some of the metal leads to equalize the capacitance throughout the clock tree.
Another technique for minimizing clock skew uses multiple buffers to drive the resistance and capacitance encountered by the clock signal. However, these buffers add propagation delays, which also cause clock skew.
With the higher operating frequencies being used in integrated circuits, it is necessary to accurately control the clock by controlling both the capacitive loading due to the metal leads and the buffering of the clock signals. In addition, as integrated circuit fabrication methods provide decreased device and metal lead dimensions in the integrated circuit, resistance is more prominent in effecting clock skew.
In the integrated circuits art, it is often difficult to test sequential circuit elements within the logic of an integrated circuit compared to testing combinatorial circuit elements. As a result, many design for testability methods have been utilized. One such design for testability is a scan path method which enables direct application of test vectors to sequential circuit elements. The sequential circuit elements are serially connected together to form a scan path. A test vector is applied from an input pin to the first sequential circuit element of the scan path. A clock (enable) signal stores the value of the test vector as it propagates through the sequential circuit elements. In essence, the sequential circuit elements function as a shift register. The output from the last sequential circuit element is compared with an expected value. In order to carry out the shift operation of the scan path input vector, the clock signals of adjacent sequential circuit elements should not be active at the same time.
In such a conventional scan path method, problems arise such as erroneous test vector outputs caused by clock skew. The clock skew is caused by the uneven layout of metal leads for each sequential circuit element of the shift register, the buffers inserted to compensate for the insufficient driving capability of the clock signal, etc. Thus, the sequential circuit elements read the input vector at different times, resulting in the failure to operate properly as a shift register.
Typically, the scan path is reordered during the layout process to minimize the chip area overhead of adding the scan path to the design. Examples of such a reordering are disclosed in U.S. Pat. No. 5,307,286 to Rusu et al. entitled “METHOD FOR OPTIMIZING AUTOMATIC PLACE AND ROUTE LAYOUT FOR FULL SCAN CIRCUITS” and U.S. Pat. No. 5,212,651 to Yabe entitled “SCAN PATH GENERATION WITH FLIP-FLOP REARRANGEMENT ACCORDING TO GEOMETRY OF LOGIC CIRCUIT.”
U.S. Pat. No. 5,307,286 (the '286 patent) discloses an integrated circuit having flip-flop circuits arranged in rows with buffers that provide signals to those flip-flops. During layout of the integrated circuit, the flip-flops are grouped in rows with similar latches and buffers in a manner that scan enable signal terminals, clock lines and other global signal lines are connected between adjacent flip-flops by abutment. Buffer values are then computed to select the correct buffers to be placed in the rows with the flip-flops.
There are disadvantages to arranging the flip-flops in rows as disclosed in the '286 patent. First, although aligning the flip-flops reduces scan path connection overhead of the chip area, it may increase the connection overhead for connections between the flip-flops and the combinatorial logic. For instance, the connection length between a combinatorial element and an adjacent flip-flop can increase when the flip-flop is aligned with other flip-flops.
Second, there may be clock skew problems between rows of flip-flops that are connected together. Initially, the rows are formed before the clock signal is distributed. Adjacent rows of flip-flops can then be connected together to form part of the scan path. The scan path connections are direct from one sequential circuit element to another. The elements in the scan path are susceptible to hold time failures due to clock skew because of the length of the direct connections between the scan elements. In addition, a clock signal provided to the buffers in one flip-flop row may be skewed with respect to a clock signal provided to the buffers of a directly connected flip-flop row. The clock signals in this case, for example, are provided from different clock buffers of the clock tree.
U.S. Pat. No. 5,212,651 (the '651 patent) discloses a method of scan path generation. The method places flip-flops in a two-dimensional plane according to original scan path data that represents a sequence according to how the flip-flops would originally be connected in the scan path. The flip-flops are then connected in a sequence that meets geometrical design requirements of a logic circuit.
The rearranging of the scan path flip-flops according to the '651 patent simply reduces the length of the scan path interconnections. Clock skew between the flip-flops is not accounted for in the '651 patent. Moreover, the clock skew between the flip-flops can be worsened by the rearranging disclosed in the '651 patent if the new arrangement sequences flip-flops that are not clocked by the same buffered clock signal.
Balanced clock tree is a common method for providing low skew clock distribution. However, even with a low skew clock distribution, hold time failures will occur in the scan path. A hold time failure occurs when the clock skew between two scan elements is greater than the propagation delay minus the hold time of the scan elements. This is becoming a significant issue in integrated circuit testing because the device propagation delays are reducing and RC induced clock skews are increasing with sub-micron technologies. Thus, there arises a significant problem for the ability to use a scan path in an integrated circuit design.
U.S. Pat. No. 5,459,736 to Nakamura entitled “SCAN PATH CIRCUIT FOR TESTING MULTI-PHASE CLOCKS FROM SEQUENTIAL CIRCUITS” and U.S. Pat. No. 5,337,321 to Ozaki entitled “SCAN PATH CIRCUIT WITH CLOCK SIGNAL FEEDBACK, FOR SKEW AVOIDANCE” address clock skewing relative to scan paths.
U.S. Pat. No. 5,459,736 (the '736 patent) discloses a scan path circuit which utilizes at least two test clock signals and additional logic to avoid a malfunction during the scan test due to clock skew. An evident disadvantage to the apparatus disclosed in the '736 patent is that the additional logic and plural clock signals increase the complexity in implementing scan testing. The additional logic and wiring of the two test clock signals will increase the amount of chip area required on an integrated circuit. The complexity of the timing control of the additional logic and the plural signals will also increase. Also, the manufacturing of the integrated circuit will become more complex since the additional logic and plural test clock signa

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