Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-10-29
2000-10-10
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
G01R 3128
Patent
active
061311731
ABSTRACT:
The invention relates to an integrated circuit, comprising a number of independent clock domains. Seam circuits are provided in the interface signals paths between the clock domains in order to be able to isolate clock domains from each other during testing. Each seam circuit comprises a feedback loop having a multiplexer and a flip-flop feeding a first input of the multiplexer, a second input of the multiplexer being connected to the seam input, an output of the feedback loop being connected to the output; so that a first state of the multiplexer allows loading of a data bit in the feedback loop via the seam input, and a second state of the multiplexer freezes the data bit in the feedback loop.
REFERENCES:
patent: 5008618 (1991-04-01), Van Der Star
patent: 5577052 (1996-11-01), Morris
patent: 6032268 (2000-02-01), Swoboda et al.
Bos Gerardus A. A.
Jacobs Jacobus A. M.
Lousberg Guillaume E. A.
Meirlevede Johan C.
Cady Albert De
Lamarre Guy
U.S. Philips Corporation
Wieghaus Brian J.
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